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Adventurer
Adventurer
9,391 Views
Registered: ‎11-09-2010

Placement algorithms

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Hi,

- I am curious to know is there any information about the algorithms Xilinx uses for placement and routing? or it is a confidental issue and can't be found in docuements.

- and I want to write my own routing algorithm based on the output of placement, I need to know about the structure of interconnection switch boxes, routing recourses.. is there such document available for this? since I couldn't find it.

 

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Adventurer
Adventurer
17,765 Views
Registered: ‎11-09-2010

Thanks,

Actually I found those information I needed in Xilinx Design Language (XLD) and Programable interconnect (PIP) documents.

 

 

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Moderator
Moderator
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Registered: ‎01-16-2013
Hi,

This is internal information. There is no public documentation related to any algorithm associated with Implementation.

User have only access to different algorithms with the help of pre defined strategies/switches.
When user use any specific switch/strategy at back end different algorithm works.

You will get the detail about each strategy in UG-904 appendix-C.

More than this all information's are confidential and not accessible for users.
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Adventurer
Adventurer
9,363 Views
Registered: ‎11-09-2010

Thanks,

What about routing resources? If I want to implement my own routing algorithm  on a design already placed by ISE, is there any special document about routing resources? ( I have already read placement output).

Because I see manual routing is allowed, then I guessed probably there should be something details about routing resources.

For example, how can I configure switch box?

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Moderator
Moderator
9,359 Views
Registered: ‎06-24-2015
Hi,

Refer to these documents for manual routing, if you are using ISE:
http://www.xilinx.com/support/sw_manuals/2_1i/download/fpedit.pdf
http://www.xilinx.com/support/documentation/sw_manuals/help/iseguide/mergedProjects/fpga_editor/html/fe_p_manual_route.htm
Thanks,
Nupur
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Moderator
Moderator
9,355 Views
Registered: ‎07-01-2015

Hi @hamze,

 

Please go through the following links:

http://www.xilinx.com/support/answers/54683.html

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_3/ug986-vivado-tutorial-implementation.pdf  (lab#3)

 

Thanks,
Arpan

Thanks,
Arpan
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Moderator
Moderator
9,353 Views
Registered: ‎06-24-2015
Also this tutorial might come handy if you are using Vivado:
http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_4/ug986-vivado-tutorial-implementation.pdf
Thanks,
Nupur
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Adventurer
Adventurer
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Registered: ‎11-09-2010

Thanks,

Actually I found those information I needed in Xilinx Design Language (XLD) and Programable interconnect (PIP) documents.

 

 

View solution in original post

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