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Explorer
Explorer
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Registered: ‎05-21-2009

Placement and routing constraint for RAM16X8S

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Hi guys,

 

I'm using a "for....generate" statement to implement a couple of RAM16X8S blocks. Since I want specific slice placement (I want it to be placed in a SLICEM at a specific position), I'm using the attribute-statement in my VHDL:

 

ATTRIBUTE LOC : string;

ATTRIBUTE LOC of inst_RAM: label is "SLICE_X0Y0";

 However, when I run synthesis, I get the following error:

 

ERROR:Pack:2811 - Directed packing was unable to obey the user design
   constraints (LOC=SLICE_X0Y0) which requires the combination of the    symbols listed below to be packed into a single SLICEM component.

 I know the attribute works for regular LUT-placement, but I'm assuming this doesn't work for implementing LUT-based RAM. What is the correct way to do this? I tried RLOC as well, but apparently this is invalid. How do I explicitly state in which slice I want to place my RAM-based LUT?

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Explorer
Explorer
5,556 Views
Registered: ‎05-21-2009

Hi bwade!

 

Thanks for the reply and for pointing me to the full error. It is indeed a packing error, sorry for the mistake in the description. When investigating the full error, I found that I made a mistake. Using the "for...generate"-statement I was accidentally trying to pack all the RAMs inside the same slice, which obviously is impossible. I just added an attribute for each implementation, which worked like a charm.

 

Thanks for pointing me in the correct direction!

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Scholar
Scholar
4,285 Views
Registered: ‎07-01-2008

That's not a synthesis error but a pack error that occurs during Map. You didn't give us the complete error message. There's usually a summary line that says why the pack could not be done. What device architecture is involved?

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Explorer
Explorer
5,557 Views
Registered: ‎05-21-2009

Hi bwade!

 

Thanks for the reply and for pointing me to the full error. It is indeed a packing error, sorry for the mistake in the description. When investigating the full error, I found that I made a mistake. Using the "for...generate"-statement I was accidentally trying to pack all the RAMs inside the same slice, which obviously is impossible. I just added an attribute for each implementation, which worked like a charm.

 

Thanks for pointing me in the correct direction!

View solution in original post

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