Placement fail (SSI partitioning failed) when using set_property USER_SLR_ASSIGNMENT
I have a large design on VU9P which has 3 SLRs. The design meets timing and works in deployment, but some of the placements are not what I was indented to be. I'm using a 2 level switching between a central unit and 16 compute units, in two steps of 1 to 4 crossbars. The central unit is in the middle SLR, while the compute units are in the bottom and top SLRs. So I want the first level switch to be on the middle SLR and the second level switches to be on the bottom/top SLRs.
However, vivado puts all the second level switch on the top SLR, even the ones for the units on the bottom SLR. I have two pipeline registers between first level and second level switches, and also 2 pipeline registers between the switches and compute units/central unit. Since I'm using reconfigurable pblocks for the compute units, I cannot make a pblock of the whole top/bottom SLR, and making a large pblock with 8 missing rectangles does not seem to be best.
I decided to use set_property USER_SLR_ASSIGNMENT, but it resulted in SSI partitioning failed, with no further details. I then used get_slrs -of_objects to check what is the placement of the units in the deign that meets timing and works, and even replicating the same SLR allocations at that design fails with the same error. Also if I set the rule for a part of one of switches, as in very small footprint, then the design works as normal, so the xdc rule is fine and isn't causing any errors. I tried full implementation or just placement strategies that are SSI oriented, to no avail.
Now is there a method to get better insights of what fails during placement? I'm thinking of adding USER_SLL_REG rules, but unless USER_SLR_ASSIGNMENT does not work without USER_SLL_REG, it shouldn't be necessary and USER_SLR_ASSIGNMENT should give enough hints to the placer.