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Registered: ‎09-07-2016

Placement of register slices

I have a medium sized design for a XCKU085 (30-50% utilization) with two SLRs.  Because of the device features I have to route AXIS buses (<200MHz) from both SLR regions to a central location. I have added two AXIS register slices in each AXIS bus to relax timing and in most cases Vivado closes timing with a small margin, but it is not robust. As soon as I add a bit of additional logic (e.g. ILA debug cores) timing tends to fail.

When I investigate the implemented design, I see that the placer has placed the two register slices close to each other with slack of 3 or more ns between them, while the path to the first register slice fails. This is very different to the behaviour shown in the Ultrafast Methodology Guide, where the placement tool distributes register slices uniformly over the path.


It seems that for the implementation strategy (Performance_Explore) it is more important to keep entities of the same hierarchy together in one SLR, then to get better timing margins.


I could now force the register slices with pblocks to specific locations, but this would be a somewhat tidious task, where I have to manually find proper spots for all registers. Is there a way (like an attribute) to tell Vivado for specific entities (e.g. register slices), that he should put more effort into finding a good placement for them?


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