cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Contributor
Contributor
838 Views
Registered: ‎08-18-2017

Placer ERROR: [#UNDEF] __HD_IS_CORE_TOP

Jump to solution

I have a design with four 8-channel ADC deserializers.  In each deserializer instance, I instantiated 2 ILAs to look a raw ADC data.  This was working fine for a few months, but now I get a placer error on the ILAs.  I'll post the relevant lines from runme.log below.  If I remove the ILAs, I can implement with no issues.  Does anyone know what the error message indicates?  I've found nothing about it in the forums or answer records.

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
ERROR: [#UNDEF] __HD_IS_CORE_TOP
ERROR: [#UNDEF] __HD_IS_CORE_TOP
ERROR: [#UNDEF] __HD_IS_CORE_TOP
ERROR: [#UNDEF] __HD_IS_CORE_TOP
ERROR: [#UNDEF] __HD_IS_CORE_TOP
ERROR: [#UNDEF] __HD_IS_CORE_TOP
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 12d03ab6f

Time (s): cpu = 00:01:46 ; elapsed = 00:01:43 . Memory (MB): peak = 1952.277 ; gain = 0.000
Phase 1 Placer Initialization | Checksum: 12d03ab6f

Time (s): cpu = 00:01:46 ; elapsed = 00:01:43 . Memory (MB): peak = 1952.277 ; gain = 0.000
ERROR: [Place 30-99] Placer failed with error: 'IO Clock Placer failed'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
Ending Placer Task | Checksum: e7256928

Time (s): cpu = 00:01:46 ; elapsed = 00:01:43 . Memory (MB): peak = 1952.277 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
60 Infos, 0 Warnings, 0 Critical Warnings and 8 Errors encountered.
place_design failed
ERROR: [Common 17-69] Command failed: Placer could not place all instances
INFO: [Common 17-206] Exiting Vivado at Thu Dec  5 14:51:48 2019...
0 Kudos
1 Solution

Accepted Solutions
Highlighted
Moderator
Moderator
474 Views
Registered: ‎05-08-2012

This issue has been reported, and has a scheduled fix in the upcomming 2020.1 release of Vivado. The error that should have been printed is listed below. The problem relates to pairs of BUFRs that drive Block RAM clock pins CLKARDCLK/CLKAWRCLK, but each BUFR is placed in a different clock region. Since BUFRs can only drive one clock region, placement errors. 

This was overcome by adjusting the ILA probes in the design. While in this case, adding ILA logic removed the error, reducing the ILA logic would be suggested. Also manually constraining the BUFRs in a design to ensure that all of their loads are within the same clock region would be another way to avoid the error.

ERROR: ADCintfc0/clk_gen[0].bufr_d (BUFR.O) is provisionally placed by clockplacer on BUFR_X0Y9
               ADCintfc3/clk_gen[1].bufr_d (BUFR.O) is provisionally placed by clockplacer on BUFR_X1Y11
ADCintfc0/ADC_ILA.ILA_FCcheck_0_A/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram (RAMB18E1.CLKARDCLK) cannot be placed
ADCintfc0/ADC_ILA.ILA_FCcheck_0_A/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram (RAMB18E1.CLKBWRCLK) cannot be placed
ADCintfc0/ADC_ILA.ILA_FCcheck_0_A/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (RAMB36E1.CLKARDCLK) cannot be placed
ADCintfc0/ADC_ILA.ILA_FCcheck_0_A/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (RAMB36E1.CLKBWRCLK) cannot be placed
ADCintfc0/ADC_ILA.ILA_FCcheck_0_A/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (RAMB36E1.CLKARDCLK) cannot be placed
ADCintfc0/ADC_ILA.ILA_FCcheck_0_A/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (RAMB36E1.CLKBWRCLK) cannot be placed
---------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
---------------------------------------------------------------------------------------------

View solution in original post

8 Replies
Highlighted
Xilinx Employee
Xilinx Employee
807 Views
Registered: ‎05-22-2018

Hi @rhc110again ,

Please attach the complete runme.log containing all the 8 errors.

Thanks,

Raj

0 Kudos
Highlighted
Contributor
Contributor
765 Views
Registered: ‎08-18-2017

Hi @rshekhaw ,

It's attached.  Sanitized the project name to PROJx, but otherwise it's the full log file.

Thanks,

Rich

0 Kudos
Highlighted
Moderator
Moderator
749 Views
Registered: ‎05-08-2012

Hi @rhc110again 

Thanks for the log. Unfortunately, there does not look to be any more information contained that narrows the issue down further. I also do not see any other reports of this message. What is the operating system used? If it is supported, this should be reported with a reproducible design.

---------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
---------------------------------------------------------------------------------------------
0 Kudos
Highlighted
Contributor
Contributor
747 Views
Registered: ‎08-18-2017

I'm running Windows10 on my native system, where I'm developing this project.  I also have a Ubuntu VM that I can try.  Will try to reproduce and respond with results.

0 Kudos
Highlighted
Contributor
Contributor
744 Views
Registered: ‎08-18-2017

I forgot to mention that I noticed there are 6 instances of the error listed in the log.  I have the same ILA instantiated twice in a module that is itself instantiated four times.  So there are 8 total instances of an idential ILA.  Seems like it places the first 2 fine, then barfs on the rest?

0 Kudos
Highlighted
Contributor
Contributor
593 Views
Registered: ‎08-18-2017

I've made another observation that may be relevant.  I opened the synthesized schematic to examine the clock connections to the ILAs, and each back to the input pin.  Each clock input is connected to an IBUFDS, which is surprising, because the code explicity instantiates and IBUFGDS in each case.  This prompted me to look back through the Synthesis log, and I found the following INFO therein:

INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 440 instances were transformed.
  FDRSE => FDRSE (FDRE, LUT4, VCC): 144 instances
  IBUFGDS => IBUFDS: 8 instances
  MUXCY_D => MUXCY: 208 instances
  MUXCY_L => MUXCY: 80 instances

A search for other reports of IBUFGDS getting "transformed" into IBUFDS revealed that most folks have this problem when they connect their clock inputs to non-CC pins.  That's not true in my case.  All the clocks are connected to CC pins; most are MRCC pins, but some are SRCC pins (which should be fine since the inputs for a specific ADC do not span multiple banks, correct???).   Any thoughts or explanations about the cause(s) or impact(s) of the "transformation?"

0 Kudos
Highlighted
Moderator
Moderator
475 Views
Registered: ‎05-08-2012

This issue has been reported, and has a scheduled fix in the upcomming 2020.1 release of Vivado. The error that should have been printed is listed below. The problem relates to pairs of BUFRs that drive Block RAM clock pins CLKARDCLK/CLKAWRCLK, but each BUFR is placed in a different clock region. Since BUFRs can only drive one clock region, placement errors. 

This was overcome by adjusting the ILA probes in the design. While in this case, adding ILA logic removed the error, reducing the ILA logic would be suggested. Also manually constraining the BUFRs in a design to ensure that all of their loads are within the same clock region would be another way to avoid the error.

ERROR: ADCintfc0/clk_gen[0].bufr_d (BUFR.O) is provisionally placed by clockplacer on BUFR_X0Y9
               ADCintfc3/clk_gen[1].bufr_d (BUFR.O) is provisionally placed by clockplacer on BUFR_X1Y11
ADCintfc0/ADC_ILA.ILA_FCcheck_0_A/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram (RAMB18E1.CLKARDCLK) cannot be placed
ADCintfc0/ADC_ILA.ILA_FCcheck_0_A/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram (RAMB18E1.CLKBWRCLK) cannot be placed
ADCintfc0/ADC_ILA.ILA_FCcheck_0_A/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (RAMB36E1.CLKARDCLK) cannot be placed
ADCintfc0/ADC_ILA.ILA_FCcheck_0_A/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (RAMB36E1.CLKBWRCLK) cannot be placed
ADCintfc0/ADC_ILA.ILA_FCcheck_0_A/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (RAMB36E1.CLKARDCLK) cannot be placed
ADCintfc0/ADC_ILA.ILA_FCcheck_0_A/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (RAMB36E1.CLKBWRCLK) cannot be placed
---------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
---------------------------------------------------------------------------------------------

View solution in original post

Highlighted
Contributor
Contributor
448 Views
Registered: ‎08-18-2017

Before I accept @marcb 's answer as the solution, I wanted to clarify that I decided to retrace my steps; in my first comment, I mentioned that these ILA's had been working for a few months, then this issue popped up.  I remembered that I previously had another ILA in my design, and that other ILA was further down the data processing path, and it was connected to my "board clock" domain.  When I added the other ILA back in, then my deserializer ILA's implemented just fine.  I can use them to capture ADC data coming out of the deserializers in the ADC-specific data clock domains (all ADC data clocks are phase-related to the board clock, but the phase relationship is unknown on each power cycle or reset).  As @marcb mentioned, that causation doesn't make much sense, but I proved it by adding/removing that other ILA a couple of times and achieving the same results.

Thanks again, Marc, for the effort to chase it down!

0 Kudos