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Observer cdv16
Observer
164 Views
Registered: ‎06-07-2019

Placing constraints on differential signals

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Hi, 

 

I have a custom IP that takes in differential signals from an external ADC via the FMC (I'm working with the Kintex KC705 board). I instantiated an IBUFDS in the verilog wrapper of this IP. ADC_SAMPLE_DIFF_IN is a 10-bit differential signal, and I need to constrain all 20 pins to the FPGA U1 pin numbers that correspond to the FMC pins. 

// Instantiation of the ADC differential data input IBUFDS 
	IBUFDS # (
    	.CAPACITANCE("DONT_CARE"),
    	.DIFF_TERM("FALSE"),
    	.IBUF_DELAY_VALUE("0"),
    	.IFD_DELAY_VALUE("AUTO"),
    	.IOSTANDARD("DEFAULT")
	) adc_diff_input_IBUFDS_inst (
	   .O(ADC_SAMPLE_DIFF_IN),
	   .I(adc_sample_in_P),
	   .IB(adc_sample_in_N)
	);

After synthesis, I went into I/O Planning view to place my constraints and noticed that

  1. Other differential signals, such as the system clock, only had one row instead of two. The negative signal didn't have its own row... it was just placed under the column/tab "Neg Diff Pair" for the positive signal. 
  2. For my ADC differential signals, ONLY ONE row (adc_sample_in_P_0[0]) had a negative signal (adc_sample_in_N_0[0])  under its "Neg Diff Pair" column. So there were a total of 19 rows for the 20 signals. 

Obviously, I need to constrain both the positive and negative signals. For example, if I need adc_sample_in_P_0[0] and adc_sample_in_N_0[0] to go to pins D26 and C26, resp. By having both signals in the same row, however, I can only constrain adc_sample_in_P_0[0] to D26. Will Vivado automatically constrain the negative pair to D26 too?

 

If the correct way to do it is for Vivado to infer the negative pair constraint, I should only have 10 rows. How do I change my I/O planning view to show the 10 rows instead of 19?

D8D9.PNGadcdiffpins.PNG

 

Thanks, 

Carlos

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1 Solution

Accepted Solutions
Observer cdv16
Observer
131 Views
Registered: ‎06-07-2019

Re: Placing constraints on differential signals

Jump to solution

 

The solution is to put the vector dimentions in the IBUDS instance name, as explained in https://forums.xilinx.com/t5/Virtex-Family-FPGAs-Archived/How-to-use-IBUFDS-OBUFDS-differential-signals-buffers-for-Virtex/td-p/63576

 

// Instantiation of the ADC differential data input IBUFDS 
	IBUFDS # (
    	.CAPACITANCE("DONT_CARE"),
    	.DIFF_TERM("FALSE"),
    	.IBUF_DELAY_VALUE("0"),
    	.IFD_DELAY_VALUE("AUTO"),
    	.IOSTANDARD("DEFAULT")
	) adc_diff_input_IBUFDS_inst[9:0] (
	   .O(ADC_SAMPLE_DIFF_IN),
	   .I(adc_sample_in_P),
	   .IB(adc_sample_in_N)
	); 

 

 

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1 Reply
Observer cdv16
Observer
132 Views
Registered: ‎06-07-2019

Re: Placing constraints on differential signals

Jump to solution

 

The solution is to put the vector dimentions in the IBUDS instance name, as explained in https://forums.xilinx.com/t5/Virtex-Family-FPGAs-Archived/How-to-use-IBUFDS-OBUFDS-differential-signals-buffers-for-Virtex/td-p/63576

 

// Instantiation of the ADC differential data input IBUFDS 
	IBUFDS # (
    	.CAPACITANCE("DONT_CARE"),
    	.DIFF_TERM("FALSE"),
    	.IBUF_DELAY_VALUE("0"),
    	.IFD_DELAY_VALUE("AUTO"),
    	.IOSTANDARD("DEFAULT")
	) adc_diff_input_IBUFDS_inst[9:0] (
	   .O(ADC_SAMPLE_DIFF_IN),
	   .I(adc_sample_in_P),
	   .IB(adc_sample_in_N)
	); 

 

 

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