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Visitor finbarrlong
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Registered: ‎06-26-2014

Port synthesis project - Implementing Multiple EDIF netlists, "Top module not found"

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HI 

I have opened a post synthesis project with 3 different EDIF (.edn and .edf) files (1 instantiated 3 times). I have added a top level file which instantiates and interconnects the associated modules. I have assigned the top level file "netlist_wrapper_top.v" to be the top level module in the design. In the <project summary> I have

Top module name:  netlist_wrapper_top.

 

Yet when I run implementation, I get the error

 

Top file was not found. Please add a top file.

 

Does anyone have any idea as to what my problem might be?

 

Finbarr

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Moderator
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Registered: ‎09-15-2016

Re: Port synthesis project - Implementing Multiple EDIF netlists, "Top module not found"

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Hi @finbarrlong

 

Yes, IP xci file is must to add whenever you add synthesized IP netlist to the project. Have a look at this AR:

https://www.xilinx.com/support/answers/69690.html

 

Regards

Rohit

Regards
Rohit
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Moderator
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Re: Port synthesis project - Implementing Multiple EDIF netlists, "Top module not found"

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Hi @finbarrlong

 

I believe you need to create a RTL project instead of post synthesis project if you are instantiating your edif in the top level file. Refer the below link, page 75 for information on this:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_3/ug896-vivado-ip.pdf

 

Regards

Rohit

Regards
Rohit
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Visitor finbarrlong
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Re: Port synthesis project - Implementing Multiple EDIF netlists, "Top module not found"

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Rohit

Thanks for the prompt reply.

I did as you suggested and now it appears that the top level file does not pick up the EDIF netlists.

My top level file, just presents a port map to the outside world with instantiations of the IP blocks (EDIF netlists)

by name. To be clear I instantiate the "dram_cont" in the top level file and the netlist "dram_cont.edn" exists in the project.

IS this correct or do I need to instantiate stub files (I thought Vivado didn't need this)? 

Thanks

Finbarr

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Re: Port synthesis project - Implementing Multiple EDIF netlists, "Top module not found"

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Hi @finbarrlong

 

You need not to add stub file here as that is used in the third party tool to synthesize whenever your IP is instantiated in the top level file. Using the stub file prevents IO buffer insertion by third party tool.

 

>>I did as you suggested and now it appears that the top level file does not pick up the EDIF netlists.

Do you mean your 'dram_cont.edn' file is out of hierarchy to top level file and the 'dram_cont' file? Your edn/edif file should be under the top level hierarchy with both 'dram_cont.edn' and 'dram_cont' at the same level hierarchy as shown below:

edif_proj.JPG

 

Make sure your edif name and the module (which is instantiated in the top level) name is the same.

 

Regards

Rohit

Regards
Rohit
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Visitor finbarrlong
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Registered: ‎06-26-2014

Re: Port synthesis project - Implementing Multiple EDIF netlists, "Top module not found"

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Hi Rohit

 

I am obviously doing something incorrect in the top level file. It is not "linking" with the module "saxi2ram" (and I assume the the other IP elements). I attach a screen dump of the source file hierarchy. I thought the top level file would "link" the "saxi2ram" instantiation to the EDIF file with the same header, but obviously not. I don't have source RTL for these IP modules. Not quite sure what I am missing here, but obviously something?

 

Thanks

Finbarr

 

Further information;

 

Top level file is "netlist_wrapper_top.v"

                 The module name in the top level file is;

                         module netlist_wrapper_top(

 

The instantiations of the IP modules in the top level file are as below;

 saxi2ram saxi2ram_cmdstatus_inst (
.clk ( pclk ) ,
.rstn ( rstn )......................................

 

saxi2ram saxi2ram_data_inst (
.clk ( pclk ) ,
.rstn ( rstn )......................................

 

saxi2ram saxi2ram_conf_inst (
.clk ( pclk ) ,
.rstn ( rstn ) .....................................

 

UNFC UNFC_INST
(
.cpurstn (rstn ),
.cpusrst (1'b0 )......................................

 

nand_phy_v3_0_top flash_phy_top_i
(
.mmcm_rst(~rstn),//i
.mmcm_clkin(fclk_2x).......................................

 

The EDIF netlists are titled as shown below.


(edif saxi2ram
(edifversion 2 0 0)
(edifLevel 0)
(keywordmap (keywordlevel 0))

 

(edif UNFC
(edifversion 2 0 0)
(edifLevel 0)
(keywordmap (keywordlevel 0))

 

(edif nand_phy_v3_0_top
(edifversion 2 0 0)
(edifLevel 0)
(keywordmap (keywordlevel 0))

 

comb_net.jpg
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Moderator
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Re: Port synthesis project - Implementing Multiple EDIF netlists, "Top module not found"

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Hi @finbarrlong

 

Try adding .xci files of the IPs to the design hierarchy.

 

Regards

Rohit

Regards
Rohit
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Visitor finbarrlong
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Re: Port synthesis project - Implementing Multiple EDIF netlists, "Top module not found"

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Hi Rohit

 

I do not have .xci files for the IP, only .edn (.edf). 

Should I have? Can I generate these files?

 

Thanks

Finbarr

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Re: Port synthesis project - Implementing Multiple EDIF netlists, "Top module not found"

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Hi @finbarrlong

 

Yes, you need to have the .xci (which have the DCP, synthesis constraints, memory initialization and simulation files) file for these IPs even in your RTL project. .xci file will be generated whenever you customize the IP (both Xilinx or User) from the IP catalog.

 

Regards

Rohit

Regards
Rohit
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Visitor finbarrlong
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Re: Port synthesis project - Implementing Multiple EDIF netlists, "Top module not found"

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Hi Rohit

Sorry for the delay in getting back to you.

Does this imply that the minimum deliverable, from an IP vendor, providing a synthesised

netlist  is a $$$.edn file and a .xci file, if one want to integrate this IP with the rest of a

design project?

Thanks

Finbarr

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Re: Port synthesis project - Implementing Multiple EDIF netlists, "Top module not found"

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Hi @finbarrlong

 

Yes, IP xci file is must to add whenever you add synthesized IP netlist to the project. Have a look at this AR:

https://www.xilinx.com/support/answers/69690.html

 

Regards

Rohit

Regards
Rohit
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Visitor finbarrlong
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Registered: ‎06-26-2014

Re: Port synthesis project - Implementing Multiple EDIF netlists, "Top module not found"

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Rohitt

 

All I get from the IP vendor is an $$.edn file. I do not receive a .xci file.

Is it possible to generate an .xci file from a $$.edn file?

 

I presume that .xci files are required for both project and non project mode flows?

 

Thanks

Finbarr

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Visitor finbarrlong
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Registered: ‎06-26-2014

Re: Port synthesis project - Implementing Multiple EDIF netlists, "Top module not found"

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Hi 

This final message in this post, is for the benefit of others, that like me may not be used to working with raw EDIF netlists, and maybe also like me find the mountains for documentation difficult to wade through to get to the details one is looking for.

 

The resolution to the original question was to;

1) Create an RTL project

2) Create a Top level file which "connects" 3 instantiations of one piece of IP with an instantiation of another piece of IP.

3) Add the EDIF netlists for both pieces of IP to your project.

4) Instantiate a "black_box" for both pieces of IP in the Top level verilog file.

 

I have still not determined if this can be implemented in a "post_synthesis" project. 

 

Regards

Finbarr 

 

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