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Explorer
Explorer
690 Views
Registered: ‎01-05-2017

[Power 33-332] warning and how to fix it

Hello I got below warning and there is no much explanation (almost no) on the internet. Does anyone know how to fix it?? I followed the steps but didn' t understand the way of fixing it. 

By the way, depending on the first tests, design works correct but I was not expecting to have any warning/error. I met this for the first time.  

 

Best wishes

 

[Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.

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Teacher
Teacher
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Registered: ‎07-09-2009

What this is saying is , as you are possibly using a big reset circuit, with unknown timing , the estimation of power the design will use is less accurate.
IMHO, as the power estimate is less than accurate anyway, its a warning that means little to nothing,
Also, IMHO, if you have a big reset circuit in an FPGA, I wonder why ? Resets add complexity, power and resources. and are generally not of use in a FPGA which is initialised at configuration,
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639 Views
Registered: ‎01-22-2015

@macellan85 

I understand [Power 33-332] to be a gentle-warning that Vivado power analysis for your design may be inaccurate.   -because, some resets appear to be asserted for long periods/percentages of time.

That is, when Vivado does the default power analysis for a design, it makes assumptions about duration and percentage-of-time that resets are asserted.  If your design is asserting resets longer and for a greater-percentage-of-time than these default settings then average power consumption for your design will be lower than what Vivado estimates.

If you are not concerned about power-analysis for your design, then you can ignore this warning.  If you are concerned about power analysis for your design, then read UG907(v2020.1), especially pages 92-94.

Cheers,
Mark

 

 

Explorer
Explorer
610 Views
Registered: ‎01-05-2017

For my complete design I' ve located a start/stop line and also a reset line, all are asserted for a single clock cycle. Each line goes to all individual submodules. But I got this warning for the first time and after removal of the reset line the warning is still there. All in all, in the end the design works very well but I was just curious about the reason.

Btw, power usage is not an issue for now

Thank you for your time @drjohnsmith markg@prosensing.com 

Best wishes 

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Explorer
Explorer
488 Views
Registered: ‎09-25-2018

Hello Xilinx experts,

I also met this warning in my design.

@drjohnsmithyou said "you are possibly using a big reset circuit." the mean of "big" is a "Long time reset asserting" or "big fanout reset signal"?

markg@prosensing.comI'm trying to modified my logic code to eliminate this warning, can you guide me some direction to work on?

@macellan85Can you share what is your method to eliminate this warning? Thank you all very much.

Best regards,

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Teacher
Teacher
466 Views
Registered: ‎07-09-2009

To clarify. a big reset circuit , I mean one that takes up a lot of space in the design, and probably not all required. The size makes meeting the timing requirements difficult,

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Registered: ‎01-22-2015

@sheng.liu 

I'm trying to modified my logic code to eliminate this warning, can you guide me some direction to work on?

If your design is passing timing analysis then you do not need to modify your code. 

If you want to eliminate the warning then you'll need to work with Vivado Power Analysis (see UG997 for a nice tutorial on doing this).  As the warning says:

[Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.

So, you will need to describe the assert times of the high-fanout nets to Vivado Power Analysis, which will eliminate the warning and allow Power Analysis to work properly.

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Explorer
Explorer
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Registered: ‎09-25-2018

Hello markg@prosensing.com 

Thank you for your advise. I've read Page 92-94 in UG907. It shows the method of how to add set_switching_activity command to control the Reset signal attribute. But I'm more confused now, because I see so many Reset Net in my design:

Untitled.png

And their properties are different, even very different. We can see the signal rate is from 0 to 100, the High level rate is from 0 to 90%, the fanout is from 1 to 1000~

I tried to roughly set the command to:

set_switching_activity -toggle_rate 100.000000 -static_probability 0.500000 [get_nets */*r?s?t*]

But it obviously doesn't work~

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Teacher
Teacher
380 Views
Registered: ‎07-09-2009

your puting a lot of effort into the power estimator tool,
which in itself is a credit to you

but be aware, the error margins on the estimator are "huge"
so be careful as to what use you put the tools output to,

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Explorer
Explorer
328 Views
Registered: ‎01-05-2017

Dear @sheng.liu 

Unfortunately it is not solved for my case yet. But as I said above, the design works very well and I ignored it for now. If you find a solution please share with us. 

Best wishes

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