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deepvision
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Registered: ‎04-23-2019

Power Optimization encountered an exception

I get the following error

[Vivado_Tcl 4-131] Power Optimization encountered an exception: ERROR: [Common 17-70] Application Exception: Power Optimization aborted at r:/wall1/workspaces/wall513/sub/REL/2020.1.1/src/shared/pwropt/core/cmd_parser.cpp:551

I use Vivado 2020.1.1

 

I didn't get this in previous versions.

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syedz
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Registered: ‎01-16-2013

@deepvision 

 

This is a crash issue. Check this AR : https://www.xilinx.com/support/answers/55854.html 

 

Make sure you are using supported OS with Vivado version. Can you share the crash log file and vivado.log file? 

If you have power optimization phase enabled in implementation, Try to disable this switch and rerun the implementation:

image.png

If that's, not the case then use the "NoBramPowerOpt" directive with opt_design:

image.png

 

--Syed

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deepvision
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Registered: ‎04-23-2019

Thanks for reply Syed.

I'm running Windows 10. This happens to almost all projects. Never seen this in previous versions.

When using "NoBramPowerOpt" all these projects works fine.

I do not have the power opt option enabled.

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syedz
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Registered: ‎01-16-2013

@deepvision 

 

The log which you shared only has synthesis information. Glad to know the directive helped. The directive disables the BRAM power optimization:

Block RAM Power Optimization enables power optimization on block RAM cells including:
• Changing the WRITE_MODE on unread ports of true dual-port RAMs to NO_CHANGE.
• Applying intelligent clock gating to block RAM outputs

 

Make sure you are using supported update with Window 10: "Microsoft Windows 10.0 1809 Update; 10.0 1903 and 1909 Update (64-bit), English/Japanese"

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug973-vivado-release-notes-install-license.pdf#page=8  

 

Strange that you are seeing the same crash for all the vivado projects. Try a simple example design that has BRAM and check if it still crashes. 

 

--Syed

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deepvision
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Registered: ‎04-23-2019

@syedz 

Yes all projects including a BRAM crashes. The following is a very simple project reading a BRAM and output the read data.


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity FIR1 is
    port (
        Clk  : in std_logic;        
        DOut : out std_logic_vector(17 downto 0)        
    );
end entity;

architecture IMPL of FIR1 is

    type s_FIR1_CoeffBuffer_type is array (0 to 99of std_logic_vector(17 downto 0);     

    -- Stage 0    
    signal s_FIR1_Coeff_0 : s_FIR1_CoeffBuffer_type := (std_logic_vector(to_signed(41,18)),std_logic_vector(to_signed(18467,18)),std_logic_vector(to_signed(6334,18)),std_logic_vector(to_signed(7509,18)),std_logic_vector(to_signed(178,18)),std_logic_vector(to_signed(15724,18)),std_logic_vector(to_signed(11478,18)),
        std_logic_vector(to_signed(10367,18)),std_logic_vector(to_signed(7971,18)),std_logic_vector(to_signed(5473,18)),std_logic_vector(to_signed(5705,18)),std_logic_vector(to_signed(9154,18)),std_logic_vector(to_signed(4290,18)),std_logic_vector(to_signed(16827,18)),std_logic_vector(to_signed(9961,18)),
        std_logic_vector(to_signed(491,18)),std_logic_vector(to_signed(2995,18)),std_logic_vector(to_signed(11942,18)),std_logic_vector(to_signed(4827,18)),std_logic_vector(to_signed(5436,18)),std_logic_vector(to_signed(13400,18)),std_logic_vector(to_signed(14604,18)),std_logic_vector(to_signed(3902,18)),
        std_logic_vector(to_signed(153,18)),std_logic_vector(to_signed(292,18)),std_logic_vector(to_signed(12382,18)),std_logic_vector(to_signed(17421,18)),std_logic_vector(to_signed(18716,18)),std_logic_vector(to_signed(727,18)),std_logic_vector(to_signed(904,18)),std_logic_vector(to_signed(5447,18)),
        std_logic_vector(to_signed(2735,18)),std_logic_vector(to_signed(14771,18)),std_logic_vector(to_signed(11538,18)),std_logic_vector(to_signed(1869,18)),std_logic_vector(to_signed(921,18)),std_logic_vector(to_signed(6676,18)),std_logic_vector(to_signed(7308,18)),std_logic_vector(to_signed(17035,18)),
        std_logic_vector(to_signed(9894,18)),std_logic_vector(to_signed(9712,18)),std_logic_vector(to_signed(4820,18)),std_logic_vector(to_signed(12331,18)),std_logic_vector(to_signed(11342,18)),std_logic_vector(to_signed(17673,18)),std_logic_vector(to_signed(4664,18)),std_logic_vector(to_signed(15141,18)),
        std_logic_vector(to_signed(7711,18)),std_logic_vector(to_signed(9262,18)),std_logic_vector(to_signed(6868,18)),std_logic_vector(to_signed(6556,18)),std_logic_vector(to_signed(8653,18)),std_logic_vector(to_signed(13671,18)),std_logic_vector(to_signed(13766,18)),std_logic_vector(to_signed(1046,18)),
        std_logic_vector(to_signed(12859,18)),std_logic_vector(to_signed(8723,18)),std_logic_vector(to_signed(9741,18)),std_logic_vector(to_signed(8538,18)),std_logic_vector(to_signed(778,18)),std_logic_vector(to_signed(12316,18)),std_logic_vector(to_signed(3035,18)),std_logic_vector(to_signed(3199,18)),
        std_logic_vector(to_signed(1842,18)),std_logic_vector(to_signed(288,18)),std_logic_vector(to_signed(11115,18)),std_logic_vector(to_signed(9040,18)),std_logic_vector(to_signed(8942,18)),std_logic_vector(to_signed(273,18)),std_logic_vector(to_signed(3657,18)),std_logic_vector(to_signed(8455,18)),
        std_logic_vector(to_signed(4814,18)),std_logic_vector(to_signed(15890,18)),std_logic_vector(to_signed(6729,18)),std_logic_vector(to_signed(5379,18)),std_logic_vector(to_signed(15350,18)),std_logic_vector(to_signed(15006,18)),std_logic_vector(to_signed(12110,18)),std_logic_vector(to_signed(5402,18)),
        std_logic_vector(to_signed(3548,18)),std_logic_vector(to_signed(638,18)),std_logic_vector(to_signed(12623,18)),std_logic_vector(to_signed(5093,18)),std_logic_vector(to_signed(963,18)),std_logic_vector(to_signed(18756,18)),std_logic_vector(to_signed(11840,18)),std_logic_vector(to_signed(4966,18)),
        std_logic_vector(to_signed(7376,18)),std_logic_vector(to_signed(13931,18)),std_logic_vector(to_signed(7317,18)),std_logic_vector(to_signed(16944,18)),std_logic_vector(to_signed(13448,18)),std_logic_vector(to_signed(5635,18)),std_logic_vector(to_signed(11323,18)),std_logic_vector(to_signed(5537,18)),
        std_logic_vector(to_signed(2547,18)),std_logic_vector(to_signed(16118,18)),std_logic_vector(to_signed(2082,18)),std_logic_vector(to_signed(3938,18)),std_logic_vector(to_signed(16541,18)));
    
    signal s_addr : integer range 0 to 99 := 0;        

begin
    process(Clk) is        
    begin
        if rising_edge(Clk) then            
            DOut <= s_FIR1_Coeff_0(s_addr);
        end if;
    end process;

    process( Clk) is    
    begin
        if rising_edge( Clk) then
            if s_addr = 99 then
                s_addr <= 0;
            else
                s_addr <= s_addr + 1;
            end if;            
        end if;
    end process;
    
end architecture;
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