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Visitor juhizo
Visitor
645 Views
Registered: ‎12-17-2018

Power optimization error

Hi,

I've tried to do MicroBlaze based design using IP Integrator with Vivado 2018.2 and 2018.3 to Numato lab Mimas A7 board. Also tried their example, and every time got this error:

[Vivado_Tcl 4-131] Power Optimization encountered an exception: ERROR: [Common 17-70] Application Exception: Power Optimization aborted at r:/wall/workspaces/wall397/sub/REL/2018.2/src/shared/pwropt/core/cmd_parser.cpp:550

 What I've done wrongly

 

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3 Replies
Xilinx Employee
Xilinx Employee
614 Views
Registered: ‎05-08-2012

Re: Power optimization error

Hi @juhizo. Which operating system is being used with Vivado? I would make sure that it is supported. If so, can a reproducible DCP be attached?


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Visitor juhizo
Visitor
584 Views
Registered: ‎12-17-2018

Re: Power optimization error

Operating System: Microsoft Windows 10 Professional (x64) Build 17763.195 (1809/RS5)

Everything related to Microblaze crashes there. Tried Numatos example code (https://numato.com/product/mimas-a7-artix-7-fpga-development-board-with-ddr-sdram-and-gigabit-ethernet#tab-sample-code) and they send even alternative code personally to test.

There is temporaly solution to use some options for optimization: (-verbose -retarget -propconst -sweep )

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Xilinx Employee
Xilinx Employee
540 Views
Registered: ‎05-08-2012

Re: Power optimization error

Hi @juhizo.

Can you attach/send an archive that reproduces the failure? I tested the MimasA7Microblaze_Helloworld example, but did not see the same problem using Windows 10. I will send a private message in case this is needed.


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