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leonardooalves
Observer
Observer
389 Views
Registered: ‎11-24-2020

Primary clock created on inappropriate pin error even using a Clock Cell

Hi, I hope you are well.

 

I am facing two critical warnings that I could not solve. I have a custom JTAG IP and I created a clock on the tck bus (Zynq ZCU102 board). However, Vivado outputs the following methodology critical warnings:

TIMING #1: A primary clock tck is created on an inappropriate pin design_1_i/xilinx_jtag_0/tck. It is recommended to create a primary clock only on a proper clock source (input port or primitive output pin with no timing arc).
TIMING #2: A primary clock tck is created on an inappropriate pin design_1_i/xilinx_jtag_0/inst/tck_buf/O. It is recommended to create a primary clock only on a proper clock source (input port or primitive output pin with no timing arc).

 

The constraints I used for this IP:

create_clock -period 40.000 -name tck -waveform {0.000 20.000} [get_pins design_1_i/xilinx_jtag_0/tck]

set_clock_groups -asynchronous -group tck -group {default_250mhz_clk1_clk_p mmcm_clkout0 mmcm_clkout1}
set_clock_groups -asynchronous -group tck_internal -group {default_250mhz_clk1_clk_p mmcm_clkout0 mmcm_clkout1 tck}

mmcm_clkout0 and mmcm_clkout1 are generated by the DDR4 IP, while the default_250Mhz_clk1 is the clock input of the DDR4 IP.

 

I tried to solve this problem by setting:

set_property CLOCK_DEDICATED_ROUTE FALSE [get_pins design_1_i/xilinx_jtag_0/tck]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_pins design_1_i/xilinx_jtag_0/inst/tck_buf/O]

But it did not work. I attached an image of the device showing that the cell type that sources the tck net is a clock type.

 

I would like to solve these warnings because I think it is generating problems when I try to connect to the JTAG via OpenOCD. It says that the IR value is 0x083a instead of 0x01 and fails to connect to the board.

 

Thank you in advance for your help.

tck_net.png
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4 Replies
drjohnsmith
Teacher
Teacher
359 Views
Registered: ‎07-09-2009

not certain I follow totaly , but

 

You have a 250 Mhz clock, coming from an IP in the design,

    as such , this is a generated clock, the tools will apply an automatic timing constraint on it , based upon the source clock and the clock circuit,

       i.e. you do not need to constrain the IP clock yourself,

 

You say the 250 MHz is already a clock in the FPGA, hence its already on a clock capable line inside the FPGA ,

   You just need to check if its on a global or a quadrant clock , in case your two blocks are not in the same quadrant, 

 

The error message is about TCK, 

    Why are you putting it through a BUFGCE ? 

         are you wanting to gate it ?

 

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leonardooalves
Observer
Observer
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Registered: ‎11-24-2020

First of all, thank you for your reply.

I attached a pdf file of the system's design to explain better what I did. Basically, I added a DDR4 IP Core to the subsystem in my block design and created an external pin on the C0_SYS_CLK input, which I renamed for default_250mhz_clk1 but had to set it for 300MHz (ZCU102 did not accept the 250MHz). The same DDR4 IP Core outputs a 50MHz clock used as the clock input of the Custom JTAG IP Core I am using. I did not add any constraints in my XDC file for the default_250mhz_clk1 as Vivado did that automatically to SI570 CLK.  Therefore, the default_250mhz_clk1 clock (Type Signal) and the DDR4 output clock (type Global clock) were both placed in the X3Y0 clock region.

 

Concerning tck (output from the JTAG Custom IP), I only created the constraints in the XDC file as mentioned in the previous post. As far as I understand, I need a clock signal output via tck bus of 25MHz (hence the 40ns period) to connect to the JTAG IP via OpenOCD. Therefore, I expected that the tck bus would derive a 25MHz clock from default_250mhz_clk1. Besides, the BUFGCE choice was defined by Vivado while doing the route placement.

 

 

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drjohnsmith
Teacher
Teacher
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Registered: ‎07-09-2009

Sorry

none of that makes any sense to me,

   the more I dig ,the more confusing,

May be some one else ,

 

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leonardooalves
Observer
Observer
325 Views
Registered: ‎11-24-2020

Sorry. Is that anything about the system you did not understand?

 

If I ignore those two critical warnings and try to connect to the board via OpenOCD, I get the following error:

 

Info : JTAG tap: riscv.ps tap/device found: 0x5ba00477 (mfg: 0x23b (ARM Ltd), part: 0xba00, ver: 0x5)
Info : JTAG tap: riscv.cpu tap/device found: 0x24738093 (mfg: 0x049 (Xilinx), part: 0x4738, ver: 0x2)
Error: riscv.cpu: IR capture error; saw 0x83a not 0x1
Warn : Bypassing JTAG setup events due to errors
Error: dtmcontrol is 0. Check JTAG connectivity/board power.
Warn : target riscv.cpu0 examination failed

 

Therefore, OpenOCD finds the Jtag tap (riscv.cpu) but fails to connect (IR capture error). I am not sure this can be caused due to the not well-constrained jtag IP core, so I would like to fix the warnings.

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