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Visitor
Visitor
9,446 Views
Registered: ‎10-05-2011

Problem ISE10. to ISE 13.

Hi all,

 

last time, i use ISE10.1 in my projects

Now,, i use ISE 13.1.

 

When i run old project on ISE 13.1. I have problems.

 

Reading NGO file "D:/Sourse FPGA/Source 13.1/10.VGA/VGATest/VGATest.ngc" ...
EXCEPTION:Xdm:FileReader.c:3040:$Id: FileReader.c,v 1.44 2010/03/15 18:33:38 jdl
   Exp $ - D:/Sourse FPGA/Source 13.1/10.VGA/VGATest/VGATest.ngc: internal read
   error around offset 479 (x1df), expected x3b ';' but found x3d '='. This
   usually occurs because the input file is corrupt.
FATAL_ERROR:NgdBuild:Portability/export/Port_Main.h:159:1.6 - This application
   has discovered an exceptional condition from which it cannot recover. 
   Process will terminate. For technical support on this issue, please open a
   WebCase with this project attached at http://www.xilinx.com/support.

Process "Translate" failed

 My project is true, I don't understand.

Can you guide me ?

 

Thanks,

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12 Replies
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Moderator
Moderator
9,445 Views
Registered: ‎06-05-2013

Hi,

 

If you do not have enough disk space on C: (regardless of where ISE is installed), synthesis generates a corrupt .ngc file.

Just try this out I hope this will help.

 

Thanks

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Visitor
Visitor
9,439 Views
Registered: ‎10-05-2011

Hi,

 

Free Space in C: is 6.73G

Is it problem ?

 

Thanks

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Highlighted
Visitor
Visitor
9,433 Views
Registered: ‎10-05-2011

Hi,

 

Now, free space in C: is 10.8 G.

but the situation is still the same

 

Thanks,

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Moderator
Moderator
9,424 Views
Registered: ‎06-05-2013

Hi,

 

 

Can you attach your files so that I can reproduce your issue at my end then I will be able to tell the debugging steps.

 

Thanks

 

-------------------------------------------------------------------------------------
For more information please refer to configuration resources https://forums.xilinx.com/t5/FPGA-Configuration/Configuration-Resources/m-p/753763/highlight/true#M5891
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Visitor
Visitor
9,419 Views
Registered: ‎10-05-2011

Hi,

 

I attach my files.

 

Thanks

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Highlighted
Moderator
Moderator
9,394 Views
Registered: ‎06-05-2013

Hi,

 

Thanks for uploading the files.

And I have seen the files in ISE 13.1.There was no error.

You try one thing create a new project and add your .vhd file and ucf file with the selection of same Device which you have selected earlier.

 

Try it once there should not be any error.

 

Thanks

 

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For more information please refer to configuration resources https://forums.xilinx.com/t5/FPGA-Configuration/Configuration-Resources/m-p/753763/highlight/true#M5891
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Visitor
Visitor
9,385 Views
Registered: ‎10-05-2011

Hi,

 

I creat a new project and add .vhd file and .ucf file with the selection of same Device. ( ISE 13.1 )

But it is error.    :(

 

Thanks.

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Moderator
Moderator
9,382 Views
Registered: ‎06-05-2013

Hi,

 

I have attached the design files which I have used.Just check it out.

 

If it still show any kind of error then let me know.

 

 

Thanks

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For more information please refer to configuration resources https://forums.xilinx.com/t5/FPGA-Configuration/Configuration-Resources/m-p/753763/highlight/true#M5891
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Visitor
Visitor
9,377 Views
Registered: ‎10-05-2011

Hi,

 

I checked it.

You can see picture in attachment.

 

ThanksStep 1.pngStep 2.pngStep 3.pngStep 4.png

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Moderator
Moderator
5,923 Views
Registered: ‎06-05-2013

Hi,

By mistaken I have attached the same file.

Use this archived project files.

Check whether the error still there.

Just open the project directly with ISE 13.1

 

Thanks

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For more information please refer to configuration resources https://forums.xilinx.com/t5/FPGA-Configuration/Configuration-Resources/m-p/753763/highlight/true#M5891
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Highlighted
Visitor
Visitor
5,906 Views
Registered: ‎10-05-2011

Hi,

 

The error still there

You can see attachment.

 

Thanks

 

Test1.png

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Xilinx Employee
Xilinx Employee
5,888 Views
Registered: ‎09-20-2012

Hi,

 

Can you try using a different machine at your end?

 

Thanks,

Deepika.

Thanks,
Deepika.
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