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Visitor
Visitor
6,610 Views
Registered: ‎01-07-2014

Problem With DDR Implementation

Hi,

 We are designing the UART -SPI to work for the DDR. Here Transmission is working perfectly and the reciever is not working correctly.

When we tried a different logic like (always@(posedge clk or negedge clk)) we are getting the following warnings with which the reciever is not even working.

 

WARNING:Par:288 - The signal rx_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:283 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.

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Xilinx Employee
Xilinx Employee
6,602 Views
Registered: ‎10-24-2013

Hi,
There are few related posts...
http://forums.xilinx.com/t5/Spartan-Family-FPGAs/Par-288-The-signal-XLXI-163-Mram-memory37-RAMD-O-has-no-load-PAR/td-p/179440

http://forums.xilinx.com/t5/Implementation/WARNING-Par-288-IBUF-has-no-load/td-p/35945
Thanks,Vijay
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Professor
Professor
6,598 Views
Registered: ‎08-14-2007

What device are you targetting?  Dual-edge clock can only be inferred for CoolRunner II CPLD's.  For all other devices, you need to instantiate DDR registers.

-- Gabor
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Visitor
Visitor
6,575 Views
Registered: ‎01-07-2014

We are using KC705 Kintex Evaluation Board.

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