03-08-2014 01:14 AM
We are designing the UART -SPI to work for the DDR. Here Transmission is working perfectly and the reciever is not working correctly.
When we tried a different logic like (always@(posedge clk or negedge clk)) we are getting the following warnings with which the reciever is not even working.
WARNING:Par:288 - The signal rx_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:283 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
03-08-2014 06:14 AM
03-08-2014 06:41 AM
What device are you targetting? Dual-edge clock can only be inferred for CoolRunner II CPLD's. For all other devices, you need to instantiate DDR registers.