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Visitor pitawask
Visitor
3,029 Views
Registered: ‎01-18-2009

Problem during pin assignment

I have written the following verilog code for a 8 - bit CPU. It completed the implementing stage without errors. When I was trying to 'assign pins' I could only see the 8 connections of the output port but could not see the two inputs 'clock' or 'run' .

 

Then I created a schematic block to represent the CPU (without the stimulus block) tried to use a schematic diagram. The two inputs were connected to input pins via ibufs and the 8 bit output port is connected to 8 output pins via bus taps. I get a error when trying to implement the design saying that 'insntance XLXI_1 (means the schematic block for the CPU in my design) cannot be resolved'.

 

If I try to implement just the 'CPU block' , highlighting the prgram for the CPU in the top lefthand window' I can implement it without any errors. Can anyone help me to solve the problem please?

 

Thanks.

 

--------------------------------------------------------

 

module CPU3(clock, run, mbr_out);
  
    input clock;
    input run;
    output rd_wr;
    output mbr_out;
reg [7:0] pc, ir, mar, mbr, dreg, mbr_out;
reg fetch_complete, mem_write;
reg[7:0] membyte[0:16];
wire clock, run;
wire [7:0] mbr_in;

main_mem mm1 (clock, mar, mbr_in, mbr_out, mem_write);

initial
begin
pc = 0;
membyte[10] = 8'b 00001010; // data 10
membyte[11] = 8'b 00001011; // data 11
membyte[12] = 8'b 00001000;// data 12
membyte[0] = 8'b 00001010; // load mem 10
membyte[1] = 8'b 00011011; // add mem 11
membyte[2] = 8'b 00111110; // store mem 14
membyte[3] = 8'b 00001110; // load mem 14
membyte[4] = 8'b 00101100; // subtract 12
membyte[5] = 8'b 00111111; //store in 15
end

always @(posedge clock)
begin
if (run)
case (fetch_complete)
1'b1 :
 begin
 ir[3:0] = mbr[7:4];
 mar[3:0] = mbr[3:0];
 case (ir)
  4'bxx00 : begin mem_write =0; mbr = mbr_in; dreg = mbr;  end // load
 4'bxx01 : begin mem_write =0; mbr = mbr_in; dreg = dreg + mbr; end // add
 4'bxx10 : begin mem_write =0; mbr = mbr_in; dreg = dreg - mbr ;end // subtract
 4'bxx11 : begin mbr = dreg; mbr_out = mbr; mem_write = 1;  end// store
 endcase
 end
1'b0 :
    begin
 mem_write=0;
 mar = pc;
 mbr= mbr_in;
 pc=pc+1;
 fetch_complete =1;
 end
endcase
end 
endmodule

module main_mem (clk, add_in, data_out, data_in, rd_wr);

input add_in, data_in, clk, rd_wr;
output data_out;
wire [7:0] add_in, data_in;
reg [7:0] data_out;
reg[7:0] membyte[0:16];
wire rd_wr;

always@(posedge clk)
begin
if(rd_wr)
membyte[add_in]= data_in;
else
data_out = membyte[add_in];
end
endmodule

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