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Visitor sbannier
Visitor
4,218 Views
Registered: ‎09-17-2012

Problem using directed routing Pin to RAM16X1D for serial IO

Hi,

 

I got a design implementing serial high speed connections (300 MHz DDR) from an Analog Devices TigerSharc DSP to a Virtex5 FX70T. The design is based on XAPP727 for Virtex4 FPGAs and has been ported to a Virtex5.

Each differential input pin pair is directly connected to a RAM16X1D (for rising edge data) and a RAM16X1D_1 (for falling edge data) primitive. These RAMs will be implemented in two LUTs each.

The routing from the input buffer to the RAM primitives has very hard timing requirements and timing analysis often fails because a lot of routing resources are already used (which I cannot change).

My plan was to use directed routing constraints from a known-good implementation run to solve the timing issues for later runs.

The FPGA editor gives me constraints like this (rising edge part only):

NET "io<0>" ROUTE="{...CRYPTIC DIRECTED ROUTING STRING...}";

INST "IO_P<0>" LOC=R6;
INST ".../inst_ram_pos/DP" LOC=SLICE_X58Y98; INST ".../inst_ram_pos/DP" BEL="A5LUT"; INST ".../inst_ram_pos/SP" LOC=SLICE_X58Y98; INST ".../inst_ram_pos/SP" BEL="B5LUT";

where "inst_ram_pos" is the name of the RAM instance.

 

With these constraints NGDBUILD will fail, because "inst_ram_pos/DP" and "inst_ram_pos/SP" is are unknown instances.

It seems like a the RAM16X1 is split up into two instances during the mapping phase, so they are both not constrainable during the NGDBUILD run because they do not yet exist there.

If I leave the "/DP" and "/SP" parts in the hierarchical path I can use only the LOC constraints and not the BEL constraints. But that leaves the mapping the freedom to switch between A5, B5 C5 and D5LUT or at least to swap pins on the slice. And that causes the ROUTE constraint to fail.

 

Has anybody any solution to this problem?

Is there a way to access the DP and SP instances during NGDBUILD run, maybe by changing the RAM16X1D ?

Is there a better way to solve the timing issues without changing the design, just by adding constraints?

 

Many thanks in advance,

Sascha

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3 Replies
Xilinx Employee
Xilinx Employee
4,208 Views
Registered: ‎07-31-2012

Re: Problem using directed routing Pin to RAM16X1D for serial IO

Why dont you try running your design using SmartXplorer to meet timing for your design. SmartXplorer runs your design through different strategies to meet timing. You can invoke the SmartXplorer from ISE GUI -> Tools -> SmartXplorer -> Launch SmartXplorer.

 

A SmartXplorer run window opens up. You can keep the default options as shown below. For Maximum Number of Strategies the 7 strategies indicate that the tool will try to run your design using 7 different methods so as to find out the best possible timing results

 

Please check this doc regarding the usage of SmartXplorer. http://www.xilinx.com/support/documentation/user_guides/ug689.pdf

Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
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Visitor sbannier
Visitor
4,203 Views
Registered: ‎09-17-2012

Re: Problem using directed routing Pin to RAM16X1D for serial IO

I already tried the SmartXplorer and it is able to meet timing under certain conditions, but even that is not reliable.

The next problem is that we are always running two synthesis / PAR runs on the same design. The only difference is the value of a top-level generic used to control output pin values after configuration. Even changing this generic leads to timing errors following a previously timing-clean run.

 

My problem is only related to routing. My FPGA uses only 40% of LUTs and FFs. The only critical paths are those differential data and clock signal. The Place and Route algorithm does not always find a correct solution for them.

 

Here are my timing constraints used for the data link.

 

# Max delay
NET IO_CLK MAXDELAY = 2000 ps; # Clock net (single ended) NET IO MAXDELAY = 2000 ps; # Net from buffer to RAM
# Timing NET "IO_CLK_P" TNM_NET = "TNM_DSP_LINK_300MHZ"; # Clock net (differential) TIMESPEC "TS_DSP_LINK_300MHZ" = PERIOD "TNM_DSP_LINK_300MHZ" 300 MHz HIGH 50%;
# Offset OFFSET = IN 583 ps VALID 1166 ps BEFORE "IO_CLK_P" RISING; OFFSET = IN 583 ps VALID 1166 ps BEFORE "IO_CLK_P" FALLING;

I got these constraints from a former colleague of me. I do not know why the MAXDELAY is set to 2000 ps, but the 583 and 1166 ps are taken from the DSP datasheet.

 

 Is there any way to tell the routing tool to route the serial data and clock signals first?

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Xilinx Employee
Xilinx Employee
4,186 Views
Registered: ‎07-31-2012

Re: Problem using directed routing Pin to RAM16X1D for serial IO

Hi sbannier,

 

It is difficult to comment on the best routing path without the design files. However you can try the autoroute feature in FPGA Editor. Open the Design in FPGA Editor and select the required net which you want to be routed first. Change the FPGA Editor to Write Mode and then click the autoreroute switch. This switch first routes the selected singal and then the entire design.

 

Now check if you are getting a new route which has lesser routing path. Now save the FPGA Design and based on the constraint rerun the design upto implementation and check if you are still getting the timing errors.


Thanks

Anirudh

PAE

Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
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