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Observer
Observer
3,623 Views
Registered: ‎04-25-2013

Problem while hardware co simulation

hi

 

I am trying to do hardware co simulation for the the convolution code i have written in VHDL using black box in Xilinx System Generator tool i am getting error During XFLOW Process due the routing restricions and available resources as i am using spartan 3e starter kit can any one help me in this regard i am attaching my files to this post.

 

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Errors reported when using spartan 3e starter kit while X flow process are as follows..........

  

Phase 1.1  Initial Placement Analysis

ERROR:Place:665 - The design has 2 block-RAM components of which 1 block-RAM

   components require the adjacent multiplier site  to remain empty. This is
   because certain input pins of adjacent block-RAM and multiplier sites share
   routing ressources. In addition, the design has 20 multiplier components.
   Therefore, the design would require a total of 21 multiplier sites on the
   device. The current device has only 20 multiplier sites.

Phase 1.1  Initial Placement Analysis (Checksum:a3ef15d4) REAL time: 4 secs 

ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

 

Mapping completed.

See MAP report file "jtagcosim_top_map.mrp" for details.

Problem encountered during the packing phase.

 

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When using nexys 2 board xc3s1200e am getting similar error

 

Phase 1.1 Initial Placement Analysis 
ERROR:Place:665 - The design has 2 block-RAM components of which 1 block-RAM 
components require the adjacent multiplier site to remain empty. This is 
because certain input pins of adjacent block-RAM and multiplier sites share 
routing ressources. In addition, the design has 28 multiplier components. 
Therefore, the design would require a total of 29 multiplier sites on the 
device. The current device has only 28 multiplier sites. 

Phase 1.1 Initial Placement Analysis (Checksum:83a2a052) REAL time: 5 secs 

ERROR:Pack:1654 - The timing-driven placement phase encountered an error. 

Mapping completed. 
See MAP report file "jtagcosim_top_map.mrp" for details. 
Problem encountered during the packing phase. 

Design Summary 
-------------- 
Number of errors : 2 
Number of warnings : 0 
ERROR:Xflow - Program map returned error code 2. Aborting flow execution...

Thanks and Regards
Teja
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3 Replies
Scholar
Scholar
3,603 Views
Registered: ‎07-01-2008

You haven't asked a question. Is there something about the error message that you would like explained?

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Observer
Observer
3,594 Views
Registered: ‎04-25-2013

hi

 

I am sorry i was not clear in my question i want to removee that error and get the hardware simulation correct i thought people will understand.

 

Thanks and Regards
Teja
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Scholar
Scholar
3,578 Views
Registered: ‎07-01-2008

The error message is saying that you have a problem with over utilization of the block ram/multiplier components. Since only one of the components can be used in each tile and you are using all  the multiplier sites there is no legal placement for the block ram. You need to either use fewer multipliers or no block ram.

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