Showing results for 
Show  only  | Search instead for 
Did you mean: 
Registered: ‎10-01-2018

Problem with clk port

Hi all, 


I am having trouble with my first steps with verilog in the FPGA Nexys 4 DDR Board. I want to output a square signal from one of the JXADC I/O, but when generating the bitstream of my code I get the following error. 


  • [DRC NSTD-1] Unspecified I/O Standard: 1 out of 3 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: clk.

Nonetheless, my clk port I am afraid is correctly defined on the constraints document: 

set_property -dict { PACKAGE_PIN W5 IOSTANDARD LVCMOS33 } [get_ports clk]; #IO_L12P_T1_MRCC_35 Sch=clk
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk];


So, what should I do? Does any one know what am I doing wrong? I will appreciate a lot your help:)

0 Kudos
3 Replies
Registered: ‎08-16-2018


- is your xst constraint file effectively used in the design? 

- is the net name correct? Verilog is case-sensitive, clk is not Clk

- open your implemented design, go to I/O view, look for your clk pin, does it say 'STANDARD I/O' in red? Then for whatever reason your constraints weren't applied to implementation. Try to apply the standard you need (this is board dependent). Save it. It will ask you to save the constraint, say yes and overwrite your constraint file. Then open the constraint file, has it changed? In that case, for whatever reason your previous constraint wasn't right.


Xilinx Employee
Xilinx Employee
Registered: ‎05-22-2018

Hi @gmhicfo,


Please check this AR# link:




0 Kudos
Registered: ‎01-16-2013



Did you apply IOSTANDARD constraint to all the ports? An easy way would be:

set_property IOSTANDARD LVCMOS33 [all_inputs]
set_property IOSTANDARD LVCMOS33 [all_outputs]


Open the elaborated or synthesized design and change the view to IO Planning as shown below to see if the IOSTANDARD constraints from your XDC file are getting considered. 





Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
0 Kudos