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asenapati
Observer
Observer
6,025 Views
Registered: ‎06-01-2016

Problem with implementation of a latch in Virtex5

Hello,

 

I intend to implement a latch using the following lines:

 

always@(*)
     begin
         if(resetz==0)
           in_cic_d1 = 0;
            
         else if(count==3'sb000)
           in_cic_d1 = out_cic_i3;
      end

 

   always@(negedge(clk_adc) or negedge(resetz))
   begin
    if(resetz == 0)
       count<=0;
    else if (!clk_adc)
       count<=count+3'sb001;
   end

 

 

Desired: if count=000, in_cic_d1 = out_cic_i3; if count is anything other than 000, in_cic_d1 should hold the value of in_cic_d1 at the previous 'count=000'.

What i see in vsim: What is desired.

What i am seeing on fpga chipscope: (Pls. find attached). The latch holds some random value.

 

How can i modify the code to get the desired response in Virtex 5?

I need to use a latch and not a flipflop. Any help would be appreciated.

 

Thanks.

asenapati

latch_fpga.png
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7 Replies
balkris
Xilinx Employee
Xilinx Employee
5,997 Views
Registered: ‎08-01-2008

check this old document for example
http://www.xilinx.com/itp/xilinx10/books/docs/xst/xst.pdf
Thanks and Regards
Balkrishan
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gszakacs
Instructor
Instructor
5,981 Views
Registered: ‎08-14-2007

The code as described uses a gated signal as the latch gate.  Whenever the counter updates, due to variance in routing delays there can be different delay times for different bits of the counter to reach the AND gate.  This means that at any clock edge where the transitioning counter outputs pass through a state you're trying to decode, you can get a glitch on the latch gate.  If you really want a latch and not to use the clock, you need to supply the gate to the latch from the Q output of a single flop.  The D equation for that flop needs to anticipate the state when the counter will be the desired value, in your case 3'b000.

 

something like:

 

always@(negedge(clk_adc) or negedge(resetz))
   begin
    if(resetz == 0)
       count<=0;
       latch_gate <= 1;
    else if (!clk_adc)
       count<=count+3'sb001;
       if (count == 3'sb111) latch_gate <= 1;
       else latch_gate <= 0;
   end

 

-- Gabor
asenapati
Observer
Observer
5,959 Views
Registered: ‎06-01-2016

@gszakacs

 

Thanks a lot for replying.

I modified the code as you mentioned.

 

always@(negedge(clk_adc) or negedge(resetz))
   begin
    if(resetz == 0)
       count<=0;
       latch_gate <= 0;
    else if (!clk_adc)
       count<=count+3'sb001;
       if (count == 3'sb111) latch_gate <= 1;
       else latch_gate <= 0;
   end

 

always@(*)
     begin
         if(resetz==0)
           in_cic_d1 = 0;
           
         else if(latch_gate)
           in_cic_d1 = out_cic_i3;                          
     end

 

Problem: Now, the latch doesn't even sample the correct value when latch_gate=1 (using ISE). I am not sure, what i am doing wrong. PFA the screenshot.

 

Thanks,

asenapati

 

latch_1.png
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asenapati
Observer
Observer
5,957 Views
Registered: ‎06-01-2016

@balkris

 

Thanks a lot. It's a very useful link.

 

I am already doing what has been mentioned in the link. But the problem is how the input to the latch are generated.

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gszakacs
Instructor
Instructor
5,935 Views
Registered: ‎08-14-2007

Judging from the ChipScope screen shot, it looks like this is an inappropriate use of a latch.  If the inputs to the latch are changing on every clock cycle, the latch won't work as intended because the latch gate shuts off a bit after the clock edge when the latch D inputs are potentially changing.  Perhaps it would help if you described why you want to use a latch and how you're going to use the outputs of the latch in the system.  Usually there will be another way to implement what you want without using a transparent latch.

-- Gabor
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asenapati
Observer
Observer
5,893 Views
Registered: ‎06-01-2016

I want to use the latch as a downsampler. A latch not a flipflop to avoid one or half cycle delay.
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gszakacs
Instructor
Instructor
5,878 Views
Registered: ‎08-14-2007

If all you want to do is avoid an extra cycle of latency, you can use a combination of a flip-flop and multiplexer to emulate the latch.  This works as long as the inputs and outputs are synchronous to the clock.  Something like:

 

always@(negedge(clk_adc) or negedge(resetz))
  begin
    if(resetz == 0)
      begin
        count<=0;
        latch_gate <= 0;
        held_data <= 0;
      end
    else if (!clk_adc)

      begin
        count<=count+3'sb001;
        if (count == 3'sb111)
          begin
            latch_gate <= 1;
          end
        else latch_gate <= 0;
        if (latch_gate) held_data <= out_cic_i3;
      end

  end
 

always@(*)
     begin
         if(latch_gate) in_cic_d1 = out_cic_i3;
         else in_cic_d1 = held_data;
     end

 

-- Gabor
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