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Visitor
Visitor
2,556 Views
Registered: ‎02-08-2017

Problem with ucf file

Hi everyone,

I have a problem that is: if I remove I/O buffers (on Process Properties - Xilinx Specific Options), then I cannot Translate my design. From the .ucf file, it says some of my I/O is not found.

 

Can you guys give my some advice

Thanks in advance

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Explorer
Explorer
2,473 Views
Registered: ‎02-08-2017

I hope I understand your question right, but my first impression would be that you have assigned some pins in UCF files with I/O ports of your design. But in your design you have removed the I/O buffers so these ports are not connected any more to any logic. It can happen that the synthesis tool remove unconnected signals.

I wish if you clarify more about your UCF PIN assignment and your design I/O ports.

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