03-25-2020 01:16 PM
While doing synthesis and implementation of my verilog design in vivado design suite 2018.3. I am facing error "[Vivado 12-1017] Problems encountered:1. Attempt to kill process failed". I am not facing this issue for other designs. Please assistant me in this. Thank you.
03-25-2020 04:59 PM
Could you try to recreate the project and launch synth/impl run again?
03-25-2020 07:26 PM
Thanks for the reply. I have tried to recreate the project and launch synth/impl and run again. But still same problem facing. I am facing this problem for only this design . All other design working fine. Mostly, probably this is not vivado software error. I think it is my design issue. I have attached my project along with this. https://drive.google.com/drive/folders/1MFI55ccBZsGf6G9GfFBly2i3uJPsxktI?usp=sharing
INFO: [Synth 8-3354] encoded FSM with state register 'present_rns_reg' using encoding 'one-hot' in module 'pure_rns' /tools/Vivado/2018.3/bin/loader: line 213: 7125 Killed "$RDI_PROG" "$@" Parent process (pid 7125) has died. This helper process will now exit
03-25-2020 07:56 PM
Hi, @chandu_sathi ,
I can see the source code and top file is pure_rns.v. What's the target device you are using?