11-23-2017 03:27 PM
Hi, I have a problem with the creation of hard macro in xilinx, since I get the following error in the map stage (it is a hard macro of a delay and an AND operation:
"ERROR:Place:835 - Given the original pre-placement, no legal placements can be found for 1 group(s). The following is the description of these group(s). The relative offsets of the components are shown in brackets next to the component names."
Note that this error does not appear in families Virtex 4, Virtex 5, and Spratan 3E, but in more current families with Virtex 7 or Artix 7 there is a problem.
Has anyone had the same?
11-23-2017 07:01 PM
Portability of macros across families is not guaranteed, because sometimes the architecture changes in ways that is not compatible. I rather think you'll need to create new macros for the series 7 devices. Going forward, you might want to migrate your designs to Vivado, because that's the only vehicle for new silicon going forward.
11-23-2017 08:31 PM
For each family I generate the macro according to its specifications, and the editor recognizes the models of FPGA to use, maybe if it is necessary to work in live more current models.