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gquan
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Registered: ‎06-11-2018

Problems with lab 3 in XUP workshop materials on Embedded System Design Flow on Zynq using Vivado 2017.4

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I am new to Vivado and am trying to test XUP labs on "Embedded System Design Flow on Zynq using Vivado" (2015x). I installed Vivado 2017.4 and successfully finished lab 1 & 2. However, when I tried lab 3, I had problems to generate the bitstream, with the screenshot for the error messages attached. Can somebody please tell me how I can solve the problem? 

 

Also, the lab 3 only has instructions on how to program customized IP (i.e. led_ip) using Verilog. Can anyone help me with the instructions and source code to program the same IP using VHDL? Thank you.

 

  

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gquan
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Registered: ‎06-11-2018

Hello harshit, 

 

Thanks for responding to my questions. In fact, I was trying to use the same constraint file downloaded from the website as you indicated. Now I found the problem: in lab 3 instruction, after step 3-1-9 to make the LED port of led_ip external, we need to change its default name from LED_0[3:0] to LED[3:0]. That solves the problem. Thank you anyway for your answer. 

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hj
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Check this AR https://www.xilinx.com/support/answers/56354.html
The error message is to notify customers that they need to set IOSTANDARD and PACKAGE_PIN, in order to protect devices from accidental damage that could be caused by the tools randomly choosing a pin location or IOSTANDARD without knowledge of the board voltage or connections.

Here is the link to source file https://www.xilinx.com/support/documentation/university/vivado/workshops/vivado-embedded-design-flow-zynq/materials/2015x/2015_2_zynq_sources.zip If you have access to this page you would be able to download it.

 

Link for all the labs and design files https://www.xilinx.com/support/university/vivado/vivado-workshops/Vivado-embedded-design-flow-zynq.html 


Thanks

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For more information please refer to configuration resources https://forums.xilinx.com/t5/FPGA-Configuration/Configuration-Resources/m-p/753763/highlight/true#M5891
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gquan
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Registered: ‎06-11-2018

Hello harshit, 

 

Thanks for responding to my questions. In fact, I was trying to use the same constraint file downloaded from the website as you indicated. Now I found the problem: in lab 3 instruction, after step 3-1-9 to make the LED port of led_ip external, we need to change its default name from LED_0[3:0] to LED[3:0]. That solves the problem. Thank you anyway for your answer. 

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gquan
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Registered: ‎06-11-2018

Hello harshit, 

 

As I mentioned in my previous post, I am also trying to find the VHDL source and instructions on how to design the customized IP (led_ip) in lab 3 on Zynq using Vivado. I was told this is supposed to be trivial, but not to me. Do you happen to know how to do it? Thank you. 

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