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Adventurer
Adventurer
1,031 Views
Registered: ‎02-08-2013

Question for Xilinx Mods

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I have a design containing connections that Vivado is allowing but this forum and the UG say are illegal. Because of the speed limits of BUFs, I needed 915MHz, I'm was connecting MMCM outputs directly to iSERDES blocks. Vivado did not indicate an implementation error and it produces a bit file. I have no hardware at this point to try it on so I'm not sure what would have happened. I made a copy of the whole project before implementing XAPP585. I was wondering if Xilinx would be interested in looking into this bug otherwise I'll just delete the project.

 

Regards, Ray Haynes, Ostendo Technologies, Inc. Carlsbad, CA
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Adventurer
Adventurer
1,324 Views
Registered: ‎02-08-2013

Sorry, my bad. I should NOT have taken posters word in this forum at face value (though some much more experienced than me). Now that I read closely UG471 page 153, it does say my connections were correct. 

 

"The only valid clocking arrangements for the ISERDESE2 block using the networking
interface type are:
• CLK driven by BUFIO, CLKDIV driven by BUFR
CLK driven by MMCM or PLL, CLKDIV driven by CLKOUT[0:6] of same MMCM or PLL
• CLK driven by BUFG, CLKDIV driven by a different BUFG
When using a MMCM to drive the CLK and CLKDIV of the ISERDESE2, the buffer types
suppling the ISERDESE2 can not be mixed. For example, if CLK is driven by a BUFG, then
CLKDIV must be driven by a BUFG as well. Alternatively, the MMCM can drive the
ISERDESE2 though a BUFIO and BUFR."

So maybe my previous design would have worked. Oh well it was fun implementing the XAPP585 with it's issues.

 

Regards, Ray Haynes, Ostendo Technologies, Inc. Carlsbad, CA

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Teacher
Teacher
1,025 Views
Registered: ‎07-09-2009

why do you say its a bug ?

 

If your constraints are meet , the tools will not error.

 

 

Can you share just your constraints file,

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Moderator
Moderator
990 Views
Registered: ‎04-18-2011
Can you share your connectivity what do you clock with the mmcm is it bufio/bufr?
Is it using the HPC connection from the mmcm?
Fmax on the clock out of the mmcm is normally pretty high
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Adventurer
Adventurer
1,325 Views
Registered: ‎02-08-2013

Sorry, my bad. I should NOT have taken posters word in this forum at face value (though some much more experienced than me). Now that I read closely UG471 page 153, it does say my connections were correct. 

 

"The only valid clocking arrangements for the ISERDESE2 block using the networking
interface type are:
• CLK driven by BUFIO, CLKDIV driven by BUFR
CLK driven by MMCM or PLL, CLKDIV driven by CLKOUT[0:6] of same MMCM or PLL
• CLK driven by BUFG, CLKDIV driven by a different BUFG
When using a MMCM to drive the CLK and CLKDIV of the ISERDESE2, the buffer types
suppling the ISERDESE2 can not be mixed. For example, if CLK is driven by a BUFG, then
CLKDIV must be driven by a BUFG as well. Alternatively, the MMCM can drive the
ISERDESE2 though a BUFIO and BUFR."

So maybe my previous design would have worked. Oh well it was fun implementing the XAPP585 with it's issues.

 

Regards, Ray Haynes, Ostendo Technologies, Inc. Carlsbad, CA

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Adventurer
Adventurer
984 Views
Registered: ‎02-08-2013
I had connected the output of the MMCM directly to the iSERDES. The output max of the PLL was 933MHz which matched the input max of the iSERDES. This lead me to believe this was a valid connection. But some experienced user in this forum planted the idea in my head that I needed to use a BUF on the connections. I should not have blindly followed that suggestion. So disregard this bug post.
Regards, Ray Haynes, Ostendo Technologies, Inc. Carlsbad, CA
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