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Contributor
Contributor
327 Views
Registered: ‎10-17-2008

RFSOC HSADC placement fails due to problem LOC definition in usp_rf_data_converter_1_0.xdc file

Hi,

I'm running Vivado 2019.1 on windows 10 doing an IP Integrator design for ZCU111 board with 2 ADCs in IQ mode and 2 DACs in IQ mode. The IP Integrator design passes all checks and synthesizes fine but fails in initial placement phase. There are 6 copies of critical warning 

  • [Vivado 12-2285] Cannot set LOC property of instance 'cpu_top_i/usp_rf_data_converter_1/inst/cpu_top_usp_rf_data_converter_1_0_rf_wrapper_i/rx0_u_adc'... Instance cpu_top_i/usp_rf_data_converter_1/inst/cpu_top_usp_rf_data_converter_1_0_rf_wrapper_i/rx0_u_adc can not be placed in HSADC of site HSADC_X0Y0 because the bel is occupied by cpu_top_i/usp_rf_data_converter_0/inst/cpu_top_usp_rf_data_converter_0_1_rf_wrapper_i/rx0_u_adc(port:). This could be caused by bel constraint conflict ["c:/Eng/AirVine/vivado/rfsoc_v1/rfsoc_v1.srcs/sources_1/bd/cpu_top/ip/cpu_top_usp_rf_data_converter_1_0/synth/cpu_top_usp_rf_data_converter_1_0.xdc":55]

The LOC property that is failing is part of the Xilinx generated .xdc file usp_rf_data_converter_1_0.xdc which defines what the location X0Y0, etc is for the data converters. Here's the lines in question from that file

set_property LOC HSADC_X0Y0 [get_cells -hier -filter {name =~ */rx0_u_adc}]
set_property LOC HSADC_X0Y1 [get_cells -hier -filter {name =~ */rx1_u_adc}]
set_property LOC HSADC_X0Y2 [get_cells -hier -filter {name =~ */rx2_u_adc}]
set_property LOC HSADC_X0Y3 [get_cells -hier -filter {name =~ */rx3_u_adc}]
set_property LOC HSDAC_X0Y0 [get_cells -hier -filter {name =~ */tx0_u_dac}]
set_property LOC HSDAC_X0Y1 [get_cells -hier -filter {name =~ */tx1_u_dac}]

Because these location properties for the converters fail the placement for a design that uses them also fails with the following message

  • [Place 30-1100] Failed to do pre-placement. Reason: Unable to find available HSADC/HSDAC sites in device.This may be due to the associated bank not having enough package pins available.

I'm happy to upload the design archive if you want it.

Please let me know how to remedy this problem.

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4 Replies
Xilinx Employee
Xilinx Employee
303 Views
Registered: ‎05-08-2012

Re: RFSOC HSADC placement fails due to problem LOC definition in usp_rf_data_converter_1_0.xdc file

Hi @reyk 

This looks similar to the messaging applied where IO constraints override a Transceiver location where the message lists a conflict caused by a "(port:)". I would suggest checking the IO PACKAGE_PIN/LOC constraints.  Do these apply to ports connected HSADC sites? If so, the HSADC site physically connected to that package pin would need to match what is in the HSADC LOC constraints. If the HSADC constraints are generated by IP, then there might be a customization option to move these to locations that match the IO constraints.


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Visitor carol@chiang
Visitor
277 Views
Registered: ‎05-17-2018

Re: RFSOC HSADC placement fails due to problem LOC definition in usp_rf_data_converter_1_0.xdc file

Thanks for your reply. I met same problem. And I realize I forgot to add buffers for these input signal. Thank you so much.

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Contributor
Contributor
270 Views
Registered: ‎10-17-2008

Re: RFSOC HSADC placement fails due to problem LOC definition in usp_rf_data_converter_1_0.xdc file

Thanks to you both for your replies.

I built a toy design with just one converter and it implements fine, so it's not a problem with the LOC constraints in the converter .xdc file.

And I realize I haven't added my top level which takes signals from the processor design and sends them to the PL for processing. This means all the signals are routed outside the chip, and with 4 converters there's not enough I/O to do this.

So looks like the placement error due to insufficient pins just manifesting as a different error message, but I'll find out with my complete design that includes the processor design with a higher top level and a PL top level module.

Best regards,

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Contributor
Contributor
240 Views
Registered: ‎10-17-2008

Re: RFSOC HSADC placement fails due to problem LOC definition in usp_rf_data_converter_1_0.xdc file

Hi Carol,

Which signals did you forget to add buffers for? The converter differential clocks? Did you add buffers in the IP Integrator design, or elsewhere?

I've added back my full 4 converters and am back to getting my pre-placement errors due to those LOC constraints in the converter .xdc file, even though I'm connecting the adc outputs and dac inputs to the logic fabric so no outside the chip I/O.

 

THanks in advance,

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