Hi,
I'm experiencing some odd behavior with RLOCs.
First: I need to specify the RLOC's in the VHDL code rather than in the UCF file. Partly because I'll be using them on units that will be replicated a large number of times.
I don't find much examples for RLOCs at all when searching the web. A main question of mine is whether RLOCs can be attached only to instantiated units or also to inferred logic. I believe the latter is true, based on having read the following in "Xilinx Constraints Guide" (cgd):
"In the Unified Libraries, you can use RLOC constraints with BUFT- and CLB-related
primitives, that is, FMAP. *You can also use them on non-primitive macro symbols.*"
(my emphasis)
"RLOC Propagation Rules
RLOC is a design element constraint and any attachment to a net is illegal. When attached
to a design element, RLOC propagates to all applicable elements in the hierarchy within
the design element."
I wish to do what is described by the last paragraph. I have found few examples on RLOCs on inferred logic, but several on primitives. Describing all my logic where I need the RLOCs in terms of primitives would be a huge work so my hope is to be able to RLOC on inferred logic.
In the following example, the RLOC on the instantiated FDCE works fine but not the one on the inferred dff:
entity dff is
port(clk, d: in std_logic; q1, q2: out std_logic);
end dff;
architecture arch of dff is
attribute rloc: string;
attribute rloc of dff_inst1: label is "X0Y0";
attribute rloc of dff_inst2: label is "X0Y0";
begin
-- the RLOC for this one doesn't work:
dff_inst1: process(clk)
begin
if rising_edge(clk) then
q1 <= d;
end if;
end process;
-- but the RLOC for this one works fine:
dff_inst2 : FDCE
generic map (
INIT => '0') -- Initial value of register ('0' or '1')
port map (
Q => q2, -- Data output
C => clk, -- Clock input
CE => '1', -- Clock enable input
CLR => '0', -- Asynchronous clear input
D => d -- Data input
);
end arch;
I don't get any warning in MAP but the Flip-Flop from dff_inst1 (translated to a DF), when I inspect it in PlanAhead after PAR, isn't placed according to its RLOC. I can't understand why.
My question could end here, but to complicate things, I have actually found one example of RLOC on inferred logic which also does work when I implement it. It is an example on some Xilinx webpage:
http://www.xilinx.com/itp/xilinx8/books/data/docs/xst/xst0044_6.html
(at the bottom)
...and the code looks like this:
architecture beh of inits_rlocs_3 is
signal tmp: std_logic_vector(3 downto 0):="1011";
attribute RLOC: string;
attribute RLOC of tmp: signal is "X3Y0 X2Y0 X1Y0 X0Y0";
begin
process (CLK)
begin
if (clk'event and clk='1') then
tmp <= DI;
end if;
end process;
DO <= tmp;
end beh;
I have implemented this and it works fine - no warnings, an the RLOCs are accounted for and the dff is placed as described by the RLOC.
I just can't really understand why it works, it shouldn't. One of my quotes above from cgd reads "RLOC is a design element constraint and any attachment to a net is illegal". And the cgd gives the VHDL attribute syntax as:
attribute rloc of {component_name|entity_name|label_name}:
{component|entity|label} is “[element]XmYn[.extension]”;
...again, offering a label as something an RLOC attribute can be assigned to, but *not* including 'signal' which is actually used above, and apparently works.
What the cgd describes, I can't get to work, but what it forbids somehow seems to work anyway.
Can someone clear things out for me?
Thanks,
Carl
