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Observer
Observer
1,118 Views
Registered: ‎12-11-2017

RTL design synthesized but not implemented correctly

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Hi everyone,

 

I am trying to probe some output signals by routing them to both the HDMI transmitter and a debug port for oscilloscope. Since ILA is not working well in my system (because of PetaLinux), I wrote a verilog module to do the job. After synthesis and implementation, I found that the schematic for my from implemented design was not correct while that from synthesized design was good. I attached source code and both schematic below. Can someone tell me what's wrong with my design?

 

Thanks!

 

Verilog code:

module hdmio_probe(
    input hdmiin_hsync,
    input hdmiin_vsync,
    input hdmiin_ce,
    input [15:0] hdmiin_data,
    output hdmiout_hsync,
    output hdmiout_vsync,
    output hdmiout_ce,
    output [15:0] hdmiout_data,
    output [7:0] test_out
    );
    
    assign hdmiout_hsync = hdmiin_hsync;
    assign hdmiout_vsync = hdmiin_vsync;
    assign hdmiout_ce = hdmiin_ce;
    assign hdmiout_data = hdmiin_data;
    
    assign test_out[7] = hdmiin_hsync; 
    assign test_out[6] = hdmiin_hsync; 
    assign test_out[5] = hdmiin_vsync; 
    assign test_out[4] = hdmiout_ce; 
    assign test_out[3:0] = hdmiin_data[3:0]; 

endmodule

Synthesized design: (Port test_out is correctly connected within the module)

synth.png

 

Implemented design: (Port test_out is not connected with anything)

impl.png

 

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Moderator
Moderator
1,395 Views
Registered: ‎05-08-2012

Hi @chenhao_7. I would suggest using the method described in the below answer record. This describes turning on the verbose messaging of opt_design, and comparing the log with the pre-opt_design (synthesized) design. From this comparison, you can trace down why the connectivity of this pins would be removed.

 

I would search for connected primitives cells that should be driving this output, and the load cells it is connected to. The log file should contain a message indicating why a cell was removed, which would either be because it has no loads, or a control pin is constant (reset stuck high).

 

 

https://www.xilinx.com/support/answers/58616.html

 

 

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Mentor
Mentor
1,093 Views
Registered: ‎02-24-2014

your test port is being optimized away during "opt_design",  almost certainly because it's not connected to your output pins..   How this is happening is impossible to guess, but you need to trace the connectivity in your source code. 

Don't forget to close a thread when possible by accepting a post as a solution.
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Observer
Observer
1,083 Views
Registered: ‎12-11-2017

Thanks for your reply! However, after checking my pin constraint file, I didn't find anything wrong with the output connectivity. Below is the relevant part of my xdc file.

# ----------------------------------------------------------------------------
# JA Pmod - Bank 13 
# ---------------------------------------------------------------------------- 
set_property PACKAGE_PIN Y11  [get_ports {test_pts[0]}];  # "JA1"
set_property PACKAGE_PIN AA8  [get_ports {test_pts[1]}];  # "JA10"
set_property PACKAGE_PIN AA11 [get_ports {test_pts[2]}];  # "JA2"
set_property PACKAGE_PIN Y10  [get_ports {test_pts[3]}];  # "JA3"
set_property PACKAGE_PIN AA9  [get_ports {test_pts[4]}];  # "JA4"
set_property PACKAGE_PIN AB11 [get_ports {test_pts[5]}];  # "JA7"
set_property PACKAGE_PIN AB10 [get_ports {test_pts[6]}];  # "JA8"
set_property PACKAGE_PIN AB9  [get_ports {test_pts[7]}];  # "JA9"
set_property IOSTANDARD LVCMOS33 [get_ports {test_pts[*]}]
set_property IOB TRUE [get_ports {test_pts[*]}]

And here is the relevant part of my block design: (External output port name is "test_pts", and the name of the port on the module is "test_out")

blk.png

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Mentor
Mentor
1,071 Views
Registered: ‎02-24-2014

Check through the Vivado log file, and look carefully for messages relating to your test port.   If it's getting optimized away, there MUST be a connectivity problem somewhere.    The tool never removes connections without a reason.

Don't forget to close a thread when possible by accepting a post as a solution.
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Highlighted
Moderator
Moderator
1,396 Views
Registered: ‎05-08-2012

Hi @chenhao_7. I would suggest using the method described in the below answer record. This describes turning on the verbose messaging of opt_design, and comparing the log with the pre-opt_design (synthesized) design. From this comparison, you can trace down why the connectivity of this pins would be removed.

 

I would search for connected primitives cells that should be driving this output, and the load cells it is connected to. The log file should contain a message indicating why a cell was removed, which would either be because it has no loads, or a control pin is constant (reset stuck high).

 

 

https://www.xilinx.com/support/answers/58616.html

 

 

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

---------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
---------------------------------------------------------------------------------------------

View solution in original post

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Highlighted
Observer
Observer
1,038 Views
Registered: ‎12-11-2017

Thanks for both of your answers!

I checked logs and the implemented design again and found the not-connected pins were optimized out. However, the output pins (on the top module) still had the desired signals connected correctly to the replica of original output register. So there is no problem now.

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