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Visitor
Visitor
5,379 Views
Registered: ‎04-20-2016

RTSTAT-5 error in Vivado 2016.2

Hello everyone,

 

I have a design that includes an OOC module as design checkpoint that is already placed and routed. Around this is some custom logic that still has to be routed.

When writing the bitstream in Vivado 2015.4 everything is fine.

I migrated my project to Vivado 2016.2 but now when I try to write the bitstream I get this error:

 

RTSTAT-5#1: 2 net(s) have a partial antenna. The problem bus(es) and/or net(s) are ...

 

and then it mentions two nets in the pre-routed design checkpoint.

 

I have tried to apply this proposed fix: http://www.xilinx.com/support/answers/54795.html

 

Unfortunately that doesn't change anything. I still get the RTSTAT-5 error. Also the -effort-level option seems to have disappeared but I don't think that has anything to do with it or am I wrong?

 

Originally my design was filling the FPGA up to the notch, so I tried a design with around 25% utilization only, which still gave this error.

 

If anyone can say anything about this or if anyone could point me in some other direction to look in, that would be great.

 

Thanks in advance

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Xilinx Employee
Xilinx Employee
4,932 Views
Registered: ‎09-20-2012

Hi @jwp

 

Are both source and loads of these 2 failing nets located with in OOC sub-module?

 

Can you share the routed checkpoints of 2015.4 and 2016.2 if possible?

Thanks,
Deepika.
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Visitor
Visitor
4,920 Views
Registered: ‎04-20-2016

Hello Deepika, thanks for your answer.

 

I'm afraid I cannot disclose the OOC sub-module... but yes, the failing nets load and sources are both in the OOC sub-module.

 

For now I have a workaround by just unrouting the whole OOC module, use that as a DCP input to my scripts and rerouting it completely, including my own part of the total design.

 

However, since the OOC module is coming from a third party, and is very timing critical. At the moment I am unable to get timing closure where the old setup would. I have no idea in what manner they achieved correct timing, but if there's any manual routing involved, I certainly don't want to figure that all out myself all over, so I'm kind of half stuck now.

 

If there is any more information that I can provide you besides the design, let me know.

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Xilinx Employee
Xilinx Employee
4,852 Views
Registered: ‎09-20-2012

Hi @jwp

 

This sounds like a tool issue as unrouting and rerouting the design helps. Can you share the implementation log file of top level design?

Thanks,
Deepika.
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Observer
Observer
195 Views
Registered: ‎01-17-2018

I have had the same error, RTSTAT-5 , related to Partial antenna, on Vivado 2018.3. It appeared on an existing, silicon-tested project, after a minor HDL modification.

Then I have changed the implementation settings:

Post-Place Phys Opt Design

  •   Is_enabled

Post-Place Phys Opt Design

  •   Is_enabled

I have re-run PAR and the Generate Bitstream  steps with these settings; and everything has completed without errors. We have also tested the new bitstream on hardware and it seems ok.

Regards,

   Tullio

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