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Explorer
Explorer
310 Views
Registered: ‎06-08-2017

RTSTAT-6#1: 2 net(s) have a partial conflict.

I'm getting this error when implementing a module out-of-context.

The module is contained within a PBLOCK. I've successfully implemented 3 other instances of this same module in adjacent PBLOCKs of the same size.

I've added the congestion report below. The design isn't particularly congested, and resource utilization is low.

I've tried using different directives in different stages of implementation, but I always get conflicting routes with the same 2 signals. I'm worried this might be a bug with the hierarchical design implementation tools (from UG946).

Any ideas on what I might try to fix the conflicting signal routes?

Thank you,

Daniel

 

report_design_analysis -congestion
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.1 (win64) Build 2188600 Wed Apr  4 18:40:38 MDT 2018
| Date         : Tue May 28 15:03:41 2019
| Host         : DESKTOP-E9F111O running 64-bit major release  (build 9200)
| Command      : report_design_analysis -congestion
| Design       : DitherLock
| Device       : xc7k160t
------------------------------------------------------------------------------------

Report Design Analysis

Table of Contents
-----------------
1. Placed Maximum Level Congestion Reporting
2. Initial Estimated Router Congestion Reporting
3. Routed Maximum Level Congestion Reporting
4. SLR Net Crossing Reporting
5. Placed Tile Based Congestion Metric (Vertical)
6. Placed Tile Based Congestion Metric (Horizontal)

1. Placed Maximum Level Congestion Reporting
--------------------------------------------

+-----------+------------------+------------+-------------------------------+------------------+---------------+------+------+------+------+------+-----+
| Direction | Congestion Level | Congestion |       Congestion Window       |    Cell Names    | Combined LUTs | LUT6 | LUT5 | Flop | MUXF | RAMB | DSP |
+-----------+------------------+------------+-------------------------------+------------------+---------------+------+------+------+------+------+-----+
| North     |                0 |        35% | (CLBLM_R_X7Y47,CLBLM_R_X7Y47) | DitherLock(100%) |            0% |  37% |   0% |   0% |   0% | NA   | NA  |
| East      |                0 |        37% | (CLBLM_R_X5Y48,CLBLM_R_X5Y48) | DitherLock(100%) |            0% |   0% |  12% |   6% |   0% | NA   | NA  |
| South     |                0 |        35% | (CLBLM_R_X5Y47,CLBLM_R_X5Y47) | DitherLock(100%) |            0% |  25% |  12% |  12% |   0% | NA   | NA  |
| West      |                0 |        37% | (CLBLM_R_X5Y47,CLBLM_R_X5Y47) | DitherLock(100%) |            0% |  25% |  12% |  12% |   0% | NA   | NA  |
+-----------+------------------+------------+-------------------------------+------------------+---------------+------+------+------+------+------+-----+


2. Initial Estimated Router Congestion Reporting
------------------------------------------------

+-----------+------------------+------------+-------------------+------------+---------------+------+------+------+------+------+-----+
| Direction | Congestion Level | Congestion | Congestion Window | Cell Names | Combined LUTs | LUT6 | LUT5 | Flop | MUXF | BRAM | DSP |
+-----------+------------------+------------+-------------------+------------+---------------+------+------+------+------+------+-----+


3. Routed Maximum Level Congestion Reporting
--------------------------------------------

+-----------+------------------+------------+-------------------+------------+---------------+------+------+------+------+------+-----+
| Direction | Congestion Level | Congestion | Congestion Window | Cell Names | Combined LUTs | LUT6 | LUT5 | Flop | MUXF | RAMB | DSP |
+-----------+------------------+------------+-------------------+------------+---------------+------+------+------+------+------+-----+
* No router congested regions found.


4. SLR Net Crossing Reporting
-----------------------------

+------------+-----------------------------+
| Cell Names | Number of Nets crossing SLR |
+------------+-----------------------------+
* The current part is not an SSI device


5. Placed Tile Based Congestion Metric (Vertical)
-------------------------------------------------

+---------------+-----------------+--------------+----------------------+------------------+---------------------+
|   Tile Name   | RPM Grid Column | RPM Grid Row | Congestion in Window |    Cell Names    | Placer Max Overlap? |
+---------------+-----------------+--------------+----------------------+------------------+---------------------+
| CLBLM_R_X7Y46 | 23              | 212          | 20%                  | DitherLock(100%) | N                   |
| CLBLM_R_X7Y47 | 23              | 211          | 18%                  | DitherLock(100%) | N                   |
| CLBLM_R_X5Y41 | 17              | 217          | 17%                  | DitherLock(100%) | N                   |
| CLBLM_R_X7Y48 | 23              | 210          | 16%                  | DitherLock(100%) | N                   |
| CLBLM_R_X7Y45 | 23              | 213          | 15%                  | DitherLock(100%) | N                   |
| CLBLM_R_X5Y40 | 17              | 218          | 14%                  | DitherLock(100%) | N                   |
| CLBLL_L_X4Y42 | 14              | 216          | 13%                  | DitherLock(100%) | N                   |
| CLBLM_R_X5Y42 | 17              | 216          | 13%                  | DitherLock(100%) | N                   |
| CLBLL_L_X4Y40 | 14              | 218          | 12%                  | DitherLock(100%) | N                   |
| CLBLL_L_X4Y41 | 14              | 217          | 11%                  | DitherLock(100%) | N                   |
+---------------+-----------------+--------------+----------------------+------------------+---------------------+


6. Placed Tile Based Congestion Metric (Horizontal)
---------------------------------------------------

+---------------+-----------------+--------------+----------------------+------------------+---------------------+
|   Tile Name   | RPM Grid Column | RPM Grid Row | Congestion in Window |    Cell Names    | Placer Max Overlap? |
+---------------+-----------------+--------------+----------------------+------------------+---------------------+
| CLBLL_L_X4Y47 | 14              | 211          | 14%                  | DitherLock(100%) | N                   |
| CLBLM_R_X5Y46 | 17              | 212          | 11%                  | DitherLock(100%) | N                   |
| CLBLM_R_X5Y47 | 17              | 211          | 11%                  | DitherLock(100%) | N                   |
| CLBLM_R_X3Y47 | 13              | 211          | 9%                   | DitherLock(100%) | N                   |
| CLBLL_L_X4Y40 | 14              | 218          | 9%                   | DitherLock(100%) | N                   |
| CLBLL_L_X4Y48 | 14              | 210          | 8%                   | DitherLock(100%) | N                   |
| CLBLM_R_X5Y48 | 17              | 210          | 8%                   | DitherLock(100%) | N                   |
| CLBLL_L_X4Y46 | 14              | 212          | 8%                   | DitherLock(100%) | N                   |
| CLBLM_R_X5Y49 | 17              | 209          | 7%                   | DitherLock(100%) | N                   |
| CLBLL_L_X4Y39 | 14              | 219          | 7%                   | DitherLock(100%) | N                   |
+---------------+-----------------+--------------+----------------------+------------------+---------------------+

 

 

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3 Replies
Xilinx Employee
Xilinx Employee
279 Views
Registered: ‎05-08-2012

Re: RTSTAT-6#1: 2 net(s) have a partial conflict.

Hi @dschussheim 

I would suggest adding the log file, as this would have more information. 

Are all the clocks using an appropriate buffer? If you have a clock driving a large number of loads, but not using dedicated clocking resources, this would cause congestion.


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Xilinx Employee
Xilinx Employee
271 Views
Registered: ‎05-22-2018

Re: RTSTAT-6#1: 2 net(s) have a partial conflict.

Hi @dschussheim ,

Also please check this AR# link, on steps to follow for debuging routing issues:

https://www.xilinx.com/support/answers/53854.html

Thanks,

Raj

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Xilinx Employee
Xilinx Employee
256 Views
Registered: ‎06-27-2018

Re: RTSTAT-6#1: 2 net(s) have a partial conflict.

Hi @dschussheim ,

First of all track down the nets with the error. Run report_route_status on implemented design (post the report here also). Check the driver/load of those nets, if they are placed outside that p-block or in another p-block, check the properties of the p-block if there is any property that is conficting or restricting the routing of those nets. I can see you are using Vivado 2018.1, you can try to run the design in the latest version also, see if anything changes. 

Please provide following files/info:-

1) vivado.log and implementation runme.log (vivado.log only if using non-project mode).

2)route status report - run report_route_status on opened implementated design and share the output.

~Chinmay

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