Like the OP, I'm also using ISE 14.7 in the design of an XC6SLX9-2tqg144, and I'm getting an error that doesn't make sense.
ERROR:Place:1108 - A clock IOB / BUFGMUX clock component pair have been found
that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock
IOB component <configin> is placed at site <P74>. The corresponding BUFG
component <configin_BUFGP/BUFG> is placed at site <BUFGMUX_X2Y1>. There is
only a select set of IOBs that can use the fast path to the Clocker buffer,
and they are not being used. You may want to analyze why this problem exists
and correct it. If this sub optimal condition is acceptable for this design,
you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote
this message to a WARNING and allow your design to continue. However, the use
of this override is highly discouraged as it may lead to very poor timing
results. It is recommended that this error condition be corrected in the
design. A list of all the COMP.PINs used in this clock placement rule is
listed below. These examples can be used directly in the .ucf file to
override this clock rule.
< NET "configin" CLOCK_DEDICATED_ROUTE = FALSE; >
P74 has a 3 pin jumper on it, and I use it as a simple configuration to switch some internal signals to a set of debug pins. Nothing fast is going on P74, it's static. Why would ISE think it's a clock? I've also gotten this in the past on a reset line, and used this to suppress it: #NET "reset_n" CLOCK_DEDICATED_ROUTE = FALSE;
But today I've commented out this reset_n line, and it doesn't appear to be causing an error any more.
Any comments on the configin issue??
