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Adventurer
Adventurer
1,540 Views
Registered: ‎04-13-2017

Reg: Locking the fpga routing

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Hi,

i want to know how to lock the fpga routing, i have routed my design and locked the region by selecting fix routing inside fpga but after implementation the routing will change even though i have fixed the routing manually. is there any better way.

1. i have done with P block, it allows change in the routing within the the P block.

2. manually i have fixed the routing ,still it is changing after new implementation.

 any better way????

 

Thanks

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-08-2012

Re: Reg: Locking the fpga routing

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Hi @yatish. The syntax you posted looks like it is ISE specific. For Vivado, there are a few ways to do this.

 

LOC constraint/property which can be found on page 256 of the Properties Guide:

set_property LOC SLICE_X0Y0 [get_cells <mux_instance_1>]

set_property LOC SLICE_X0Y0 [get_cells <mux_instance_2>]

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_1/ug912-vivado-properties.pdf#page=256

 

Setting a Relatively Placed Macro (RPM), which can be found on page 166 of the Constraints Guide.

create_macro mac_1

update_macro mac_1 {<mux_instance_1> X0Y0 <mux_instance_2> X0Y0}

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_1/ug903-vivado-using-constraints.pdf#page=166

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-08-2012

Re: Reg: Locking the fpga routing

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Hi @yatish. There are a few resources for directed routing constraints. The below AR details that the IS_ROUTE_FIXED, IS_LOC_FIXED, and IS_BEL_FIXED are needed. 

 

https://www.xilinx.com/support/answers/59242.html

 

Does your current process use the same constraints?

 

Also page 138 of the Implementation Guide has more information on directed routing:

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_1/ug904-vivado-implementation.pdf

 

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Adventurer
Adventurer
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Registered: ‎04-13-2017

Re: Reg: Locking the fpga routing

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Hi,

i came to know something incremental compile, i saw some videos how to do that.

by using this fpga routing won't change ??????

 

i'm gong through the ug904 doc

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Moderator
Moderator
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Registered: ‎01-16-2013

Re: Reg: Locking the fpga routing

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@yatish,

 

Check this link to know about incremental compile in vivado: 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_1/ug904-vivado-implementation.pdf#page=94

 

Also check lab2 and lab3 in below tutorial: 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_1/ug986-vivado-tutorial-implementation.pdf

 

--Syed

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Adventurer
Adventurer
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Registered: ‎04-13-2017

Re: Reg: Locking the fpga routing

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Thank you

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Adventurer
Adventurer
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Registered: ‎04-13-2017

Re: Reg: Locking the fpga routing

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Hi @syedz

i have used below attribute to fix the loc of component i'm using in my design.

 ATTRIBUTE LOC OF delayblock : LABEL IS "SLICE_X"&INTEGER'image(Xoff)&"Y"&INTEGER'image(Yoff+i);

this attribute will use 1 mux in a CLB and it will move to next CLB.

how can i tell tool to use all the muxes in a CLB ?????

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-08-2012

Re: Reg: Locking the fpga routing

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Hi @yatish. The syntax you posted looks like it is ISE specific. For Vivado, there are a few ways to do this.

 

LOC constraint/property which can be found on page 256 of the Properties Guide:

set_property LOC SLICE_X0Y0 [get_cells <mux_instance_1>]

set_property LOC SLICE_X0Y0 [get_cells <mux_instance_2>]

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_1/ug912-vivado-properties.pdf#page=256

 

Setting a Relatively Placed Macro (RPM), which can be found on page 166 of the Constraints Guide.

create_macro mac_1

update_macro mac_1 {<mux_instance_1> X0Y0 <mux_instance_2> X0Y0}

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_1/ug903-vivado-using-constraints.pdf#page=166

 

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