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Newbie
Newbie
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Registered: ‎04-25-2019

Regading IDELAYCTRL issue in Vivado IDE

I have attched the code in text file format, where we use IDELAYCTRL.

The bit file will get generate with the following critical warnings.

pic3.PNG

Hardware used: Kintex 7 - xc7k325tffg676-1

Please provide the solution.

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Moderator
Moderator
311 Views
Registered: ‎03-16-2017

Re: Regading IDELAYCTRL issue in Vivado IDE

hi @meg36 ,

Have a look into this thread. https://forums.xilinx.com/t5/Other-FPGA-Architectures/How-to-set-ODELAYE2-REFCLK-FREQUENCY-Attribute/td-p/922941

This may help you out. 

You will have to set the clock using create_clock constraint for ref_clock.

 

Regards,
hemangd

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