07-02-2021 12:51 AM
This is my first time trying to post here, so please let me know I am missing something.
I am working on a project involving implementing a partitioned design on the vu37p. The main flow of the project is to:
I have read through the UG905-Hierarchical Design and UG909-Partial Reconfiguration and due to the bottom-up nature of the flow, I have determined that my objective is more closely align to the one described in the HD flow.
I have successfully compiled a few OOC modules without specifying the clock port and link them up in a top-level module (go through synth, place, and route).
However, when I add the clock constraint to the OOC module, a "Failed to do clock region partitioning" appears when I try to route the top-level module. Here comes the difficulty, when I compile the OOC module separately, I need to specify the clock port via "create_clock" to obtain an accurate timing estimation (for analysis).
I have read up on the two properties "HD.CLK_SRC" and "HD.PARTPIN_LOCS" and seem to require knowledge of the exact tile and clock buffer used when doing the OOC flow. I have tried both properties but the result dcps still causes the same error when applied in the top-level module placing flow. So my questions are:
Is there any way I can have the TCL scripts for the flow in UG905 for reference which is mentioned on page 20.
Thanks ahead for any help.
07-20-2021 08:53 AM
For 4, contact your Xilinx or Avnet FAE.
For 1 and 2, have you tried instantiating a BUFG (or variant) in your OOC?
I cannot help on 3.
On 4, it looks good to me--but that is from a 10,000 foot view.
The create_clock command is a command that specifies the properties of the signal used as a clock. It has been awhile, but if you aren't putting an OOC create_clock constraint, you may want to do that (possibly with a BUFG instantiation or similar). Synthesis is timing driven so having a clock defined during OOC synthesis will help improve results (in general).
Anyway, I hope somebody from Xilinx responds....but for this type of question, you would have the best luck with a Xilinx FAE with lots of FPGA experience.