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Observer
Observer
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Registered: ‎05-05-2020

Regarding i/o pins

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hello,

suppose if nearly 200 i/o pins your design, how to assign an input and port ports in your i/o planning schematic.

Thank You

Regards,

Nagi

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Xilinx Employee
Xilinx Employee
155 Views
Registered: ‎05-22-2018

Re: Regarding i/o pins

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Hi @nagi12 ,

In addition to Hong post, please check this Video on IO planning:

https://www.xilinx.com/video/hardware/i-and-o-planning-overview.html

Thanks,

Raj

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Moderator
Moderator
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Registered: ‎11-04-2010

Re: Regarding i/o pins

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Hi, @nagi12 ,

If your board has been designed, you can assign Package Pin to IO by referring to UG899  (I/O Planning part)

If your just need to have a test, you can run synth/impl directly and read the Package Pin property back.

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Xilinx Employee
Xilinx Employee
156 Views
Registered: ‎05-22-2018

Re: Regarding i/o pins

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Hi @nagi12 ,

In addition to Hong post, please check this Video on IO planning:

https://www.xilinx.com/video/hardware/i-and-o-planning-overview.html

Thanks,

Raj

View solution in original post

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