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363 Views
Registered: ‎11-14-2018

Relation between Implementation view and physical place & route

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Hello, 

I have some questions regarding implementation in Zynq7000 FPGA via VIVADO flow:

i) Is the implemented design scheme physically related to the way placement and routing is performed into the FPGA? Say I'm trying to implement two identical modules; can I assure they really are as far as their drawings look the same in the implemented design viewer? Are LUTs and wires physically placed and shaped  where they look in the scheme?

ii)  Does the same RTL code always transform into the same bitsream, and (regarding the previous question) is this bitstream always implemented the same way in two identical (same model) FPGAs?

Thank you all in advance and best regards,

Guillermo

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Teacher drjohnsmith
Teacher
352 Views
Registered: ‎07-09-2009

Re: Relation between Implementation view and physical place & route

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regarding ii, No.

Unless you RTL at the primative level ,and lock everythgin down, then , maybe. But your fighting the tools, so good luck.

 

This is the sort fo questoin we get to do with ring oscilators and such like, where th euser has desinged a set of LUT's to have a fixed delay. Its a world of pain.

 

In general, the tools work to meet your constraints, and stop.

During the optimisation procese, there are various points in the algorithums that they can use a random element, its all part of the aneeling and such flows... A BIG toppic I only know the tip of.

I also think , there are parts of the bit file, with info such as machine built on or user ID number, or time stamps, that might not get programmed into the chip but are present in th ebit file.

To add to the confusoin, there are variosu htings like Cache used and stored in the project files , so a new build on a machine without access to these files, might produce a different result.

So nope, the bit file can and does change between runs for the same vhdl.

 

Regarding 1)

Your fighting the tools.

  A route in one area of the chip, might / does have a different proergatoin delay to a similar looking route in anothe rpart fo the fpga. Thats what the tools take into account for you. As a simple example, look  at the different delays for clock to out of the different IO pins.

Add to that, do yo have a clock ? if so  , the route of that to two different areas of th echip will be different timming, 

Again the tools take care of that for you ,

 

so just because to mona lesa pictures look the same, they might not be the same, same with the fpga.

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

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Teacher drjohnsmith
Teacher
353 Views
Registered: ‎07-09-2009

Re: Relation between Implementation view and physical place & route

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regarding ii, No.

Unless you RTL at the primative level ,and lock everythgin down, then , maybe. But your fighting the tools, so good luck.

 

This is the sort fo questoin we get to do with ring oscilators and such like, where th euser has desinged a set of LUT's to have a fixed delay. Its a world of pain.

 

In general, the tools work to meet your constraints, and stop.

During the optimisation procese, there are various points in the algorithums that they can use a random element, its all part of the aneeling and such flows... A BIG toppic I only know the tip of.

I also think , there are parts of the bit file, with info such as machine built on or user ID number, or time stamps, that might not get programmed into the chip but are present in th ebit file.

To add to the confusoin, there are variosu htings like Cache used and stored in the project files , so a new build on a machine without access to these files, might produce a different result.

So nope, the bit file can and does change between runs for the same vhdl.

 

Regarding 1)

Your fighting the tools.

  A route in one area of the chip, might / does have a different proergatoin delay to a similar looking route in anothe rpart fo the fpga. Thats what the tools take into account for you. As a simple example, look  at the different delays for clock to out of the different IO pins.

Add to that, do yo have a clock ? if so  , the route of that to two different areas of th echip will be different timming, 

Again the tools take care of that for you ,

 

so just because to mona lesa pictures look the same, they might not be the same, same with the fpga.

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

View solution in original post

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Xilinx Employee
Xilinx Employee
350 Views
Registered: ‎05-22-2018

Re: Relation between Implementation view and physical place & route

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Hi gds@unizar.es ,

From both of your questions, it seems that you query is regarding Vivado tool repeatability. Please check this AR# link:

https://www.xilinx.com/support/answers/61599.html

Thanks,

raj

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345 Views
Registered: ‎11-14-2018

Re: Relation between Implementation view and physical place & route

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Thank you, drjohnsmith

And at least regarding LUT placement? Are they physically placed where they look inside the FPGA? For example say I lock two LUTs into the cells X0Y0 and X40Y0; will these be really separated 40 whatever-distance-units?
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Teacher drjohnsmith
Teacher
318 Views
Registered: ‎07-09-2009

Re: Relation between Implementation view and physical place & route

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probably, but that distance delay will / can be different to another 40 U length,

so does not tell you much.
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
307 Views
Registered: ‎09-17-2018

Re: Relation between Implementation view and physical place & route

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No, and no.

The views in Vivado are a software programmer's view of the device, in an effort to aid the designer.  Some images are derived from the actual tapeout, but you have no way of verifying, unless you tear apart a device, and de-layer it, taking images (reverse engineer).

I used to call them "cartoons" but some Xilinx engineers felt insulted.  As I no longer work for Xilinx, I still will refer to them as cartoons, if only to emphasize they are intended to illustrate, not instruct, nor demonstrate.  "Cartoon" is not an insult...

Depending on the design, the implementation will vary in terms of routing, and of couse, the bitstream.  Only identical designs, in identical devices, at the same speed grade, using the same release version of Vivado would be expected to be identical, but even then, there might be differences as the tools themselves may not be identical (later versions may have patches to bugs).  There is not supposed to be any random behavior in Vivado, as the new tools do not use a random seed as was used in ISE.  In ISE, even identical designs led to differences no matter what you did with options, etc.

l.e.o.