cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
yukkmn
Observer
Observer
809 Views
Registered: ‎03-31-2019

Removed by implementation...

Jump to solution

Hello, Everyone.

I want to get information why module removed. How can I get these?
I checked message about implementation. But there are nothing about removed module. There are only about synthesis.

Attempt
Many modules are removed by synthesis. I want to keep some modules and some wires. I used "keep_hierarchy" to avoid this matter.
Next, when I tried implementation, a lot of modules were removed by it.
I think what I force keep module from synthesis is no meaning for implementation.

Thanks.

Tags (2)
0 Kudos
Reply
1 Solution

Accepted Solutions
yukkmn
Observer
Observer
726 Views
Registered: ‎03-31-2019

Thank you for replying this thread.

Sorry, I resolved this problem in myself.
When I checked report_clocks, I found the wire is not used to clock.
I can't understand why the wire is not seen clock, but this matter is resolved.

P.S.
To avoid this problem, I write create_clock for the wire.

View solution in original post

5 Replies
watari
Teacher
Teacher
798 Views
Registered: ‎06-16-2013

Hi @yukkmn 

 

Would you refer vivado log file, first ?

I'm sure that you can find the reason in log file.

 

Best regards,

0 Kudos
Reply
hongh
Moderator
Moderator
789 Views
Registered: ‎11-04-2010

Hi, @yukkmn ,

For implementation, unused modules are removed during opt_design.

You can try to print more information in opt_design:

opt_design -verbose 

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Reply
graces
Moderator
Moderator
757 Views
Registered: ‎07-16-2008

Just to add you can also enable -debug_log option of opt_design to dump more details with regards to removal. The removal is typically caused by loadless or sourceless connectivity.

If you want to preserve the module anyway, you can apply DONT_TOUCH property, which will take effect in implementation as well.

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Reply
yukkmn
Observer
Observer
727 Views
Registered: ‎03-31-2019

Thank you for replying this thread.

Sorry, I resolved this problem in myself.
When I checked report_clocks, I found the wire is not used to clock.
I can't understand why the wire is not seen clock, but this matter is resolved.

P.S.
To avoid this problem, I write create_clock for the wire.

View solution in original post

syedz
Moderator
Moderator
654 Views
Registered: ‎01-16-2013

@yukkmn 

 

Thanks for the update. Please close this thread by marking your above post as "Accept as solution"

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
0 Kudos
Reply