09-13-2017 11:39 PM
I'm working on a quite big fpga design for a XC7VX690T-2 and have some questions regarding implementation strategies for timing critical designs. The design consists of a Xilinx PCIe DMA IP (non timing-critical), some accelerators with lots of AXI DMAs (non timing-critical yet), some interconnects (one AXI Interconnect for CSR, one AXI SmartConnect for high performance data) and a quite timing critical memory controller IP. This IP needs to run on 312.5 MHz to enable high memory bandwidths and has high internal data busses (512 bit for TX, 512 bit for RX). In some implementation runs, P&R is able to route the whole design - with the help of performance optimized strategies for synthesis and implementation. In other runs it fails to route with quite small WNS = -0.05. Most parts of my design are fix: I don't want to touch the PCIe DMA IP nor the timing critical memory controller IP, and if I find a good routing solution for these subblocks, I would like to save and reuse placement and routing of these IPs. At the moment I use pblocks to structure my subblocks on-chip, so that they don't interfere - but this doesn't seem to help, as some implementation runs fail to meet timing requirements. Furthermore I tried to save a design checkpoint after implementation and use it, but this also doesn't seem to solve my problems. Note that I only want to fix some subblocks, while other subblocks need to be rerouted everytime, since I need to add lots of modules to the interconnects etc.
I appreciate your help, dommynik.
09-13-2017 11:49 PM - edited 09-13-2017 11:52 PM
Incremental compilation should help. Check "Incremental Compile" at page 93 in below implementation user guide:
This Answer record has information on using incremental compilation in your design: