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khaalidi
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Registered: ‎01-20-2021

Ring oscillator frequency is too high (GHz 😲) and much different with consecutive readings

If a bit file is created already and we program the FPGA once , then power off , and write the bit file again, Will the logic be in the same location(Same Slices and CLB) on the FPGA as the first time?

I'm trying to create a Ring Oscillator based PUF. And first I'm analyzing of the ring oscillator.

It should be a value (between 180MHz-400MHz ) with very small standard deviation with previous readings.

Since the frequency of a ring oscillator is determined by the placement and routing, but also by the Process/Voltage/Temperature (PVT). For process, this means that even if two different FPGAs are programmed with the same bitstream, since they can have different process, they will result in different frequencies.

But my readings are :

  1. 16351469/0.5ms,
  2. 17275163 /0.5ms,
  3. 18198823/0.5ms,
  4. 19122602/0.5ms,
  5. 20046322/0.5ms,
  6. 20970099/0.5ms,
  7. 21926595/0.5ms,
  8. 22850271/0.5ms,
  9. 23774049/0.5ms,
  10. 24697803 /0.5ms

I read the frequency 10 time , after each 500us

 

Even I constrained the Ring Oscillator in pblock, each time I reprogram the fpga, the frequency is very very different and very high (in GHz) on the same FPGA using the same bitstream. 

 

My design is as follows:

IyF9s.pngQZcwR.png

 

 

 

 

❝Analogue by birth, Digital by design.❞
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drjohnsmith
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joancab
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Yes, the bitstream is the configuration of each and everyone of the cells. There is no space for any randomness of placement. When you implement your design in Vivado, one of the most time-consuming tasks is the P&R (place and route) that decides where things go and how to connect them. There is probably more than one valid implementation for a given design, but timing and dynamic performance would change and might not be valid even if placed and connected. So, another reason to have a defined placement.

khaalidi
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@drjohnsmith wrote:

It must be that time of year again when final year projects kick off...

Sorry could not resist..

do these help 

https://forums.xilinx.com/t5/Other-FPGA-Architecture/How-to-implement-a-ring-oscillator-with-routings-of-FPGA-Where/td-p/768444

https://forums.xilinx.com/t5/Implementation/Ring-Oscillator-Issue/td-p/939388

http://forums.xilinx.com/xlnx/attachments/xlnx/EDK/27322/1/HighSpeedTrueRandomNumberGeneratorsinXilinxFPGAs.pdf

https://forums.xilinx.com/t5/Versal-and-UltraScale/Gated-ring-oscillator/td-p/804374

 

 



I know how a Ring Oscillator works. I know what CLBs , Slices are and how they work.

My issue is that my Ring Oscillator frequency is different each time I turn off the FPGA board or reprogram it. Even though I made a pblock and assigned the Ring Oscillator logic into that pblock so that Place and Route always place them where I want it.

❝Analogue by birth, Digital by design.❞
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khaalidi
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@joancab wrote:

Yes, the bitstream is the configuration of each and everyone of the cells. There is no space for any randomness of placement. When you implement your design in Vivado, one of the most time-consuming tasks is the P&R (place and route) that decides where things go and how to connect them. There is probably more than one valid implementation for a given design, but timing and dynamic performance would change and might not be valid even if placed and connected. So, another reason to have a defined placement.



Thanks that cleared my confusion.

So that means for the same bitstream all my logic is placed in the same Cells and Ring Oscillator frequency must be the same each time I turn off the FPGA board or reprogram it.

 

Now I created a pblock and assigned the Ring Oscillator logic into that pblock, But I still read different value of the frequecny each time I turn off the FPGA board or reprogram it.

 

❝Analogue by birth, Digital by design.❞
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avrumw
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A pblock restricts the place and route (implementation) as to where it places certain elements. However, once place and route is done, the placement of the cells (and the routes between them) are fixed - regardless of whether the were chosen freely by the placer/router or guided by the pblock. For this bitstream (which is the output of the place and route process), all the cells and routes are in fixed locations.

So that means that the position of the placement of the cells and the routing between them remain the same as long as you don't change the bitstream. This includes powering-off and powering-on the FPGA, as long as the same bitstream is loaded each time.

But, that doesn't mean the frequency will be "the same". The frequency of a ring oscillator is determined by the placement and routing, but also by the Process/Voltage/Temperature (PVT). For process, this means that even if two different FPGAs are programmed with the same bitstream, since they can have different process, they will result in different frequencies.

The other two (V and T) also matter. The voltage of your board isn't likely to change much over time. However the temperature here is the die temperature - the temperature of the actual transistors. But, when running, the die itself dissipates power, which warms up the die. So the temperature of an FPGA will not only vary with the temperature of the room, but also the temperature of the die due to heat dissipation. The most obvious disruption will be when you power down the FPGA. The longer it is powered up, the warmer it will get (until it reaches thermal equilibrium). When you turn it off it will start cooling down (until it reaches the temperature of the room - at least asymptotically).

So this could account for different frequencies between power cycles.

Avrum

khaalidi
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@avrumw wrote:

A pblock restricts the place and route (implementation) as to where it places certain elements. However, once place and route is done, the placement of the cells (and the routes between them) are fixed - regardless of whether the were chosen freely by the placer/router or guided by the pblock. For this bitstream (which is the output of the place and route process), all the cells and routes are in fixed locations.

So that means that the position of the placement of the cells and the routing between them remain the same as long as you don't change the bitstream. This includes powering-off and powering-on the FPGA, as long as the same bitstream is loaded each time.

But, that doesn't mean the frequency will be "the same". The frequency of a ring oscillator is determined by the placement and routing, but also by the Process/Voltage/Temperature (PVT). For process, this means that even if two different FPGAs are programmed with the same bitstream, since they can have different process, they will result in different frequencies.

The other two (V and T) also matter. The voltage of your board isn't likely to change much over time. However the temperature here is the die temperature - the temperature of the actual transistors. But, when running, the die itself dissipates power, which warms up the die. So the temperature of an FPGA will not only vary with the temperature of the room, but also the temperature of the die due to heat dissipation. The most obvious disruption will be when you power down the FPGA. The longer it is powered up, the warmer it will get (until it reaches thermal equilibrium). When you turn it off it will start cooling down (until it reaches the temperature of the room - at least asymptotically).

So this could account for different frequencies between power cycles.

Avrum



Thanks for the detailed answer.  

Even I constrained the Ring Oscillator in pblock, each time I reprogram the fpga, the frequency is different on the same FPGA using the same bitstream. 

This made me think that , the  synthesizer has optimized the design into a single gate instead of chain of NOT gates. 

I added few  synthesis attributes to the design and the Schematic is what I expect.  But still after the implementation, the Schematic  is a single LUT2, meaning that the implementation has optimized the design. I'm looking for some ways to restrict the implementation to optimize the design.

Could the die temperature be that much that could change the frequency like this:  

16351469, 17275163, 18198823, 19122602, 20046322, 20970099, 21926595, 22850271, 23774049, 24697803

I read the frequency 10 time , after each 500us

 

After Synthesis,

After SynthesisAfter Synthesis

After Implementation,

 

schematic-page-001.jpg

 

Then I added (* dont_touch = "true" *) attribute and now the Implementation schematic is the same.

❝Analogue by birth, Digital by design.❞
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joancab
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You need to tell vivado not to be that smart.

when you say "different frequency", can you provide values to see, if we talk of a few % or a factor of 3?

bruce_karaffa
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A one LUT oscillator may toggle faster than the output buffer can toggle. 

khaalidi
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@joancab wrote:

You need to tell vivado not to be that smart.

when you say "different frequency", can you provide values to see, if we talk of a few % or a factor of 3?



The Ring Oscillator runs for 0.5ms then I reset the frequency counter from the controller and after 1000us read again.

16351469, 17275163, 18198823, 19122602, 20046322, 20970099, 21926595, 22850271, 23774049, 24697803

❝Analogue by birth, Digital by design.❞
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khaalidi
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@bruce_karaffa wrote:

A one LUT oscillator may toggle faster than the output buffer can toggle. 



My Verilog design is parametric , I can increase the the chain of NOT gates just by changing a parameter.  I just want to see the basic Ring Oscillator (3 not gates) with good results. 

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joancab
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Are those figures (16351469, 17275163, 18198823, etc) counts / 0.5 ms? Accumulated? So f = (17275163 - 16351469) / 0.5 ms = 1.8 GHz? FPGA pins don't respond at that frequency I'm afraid. you might have that frequency inside but to observe it outside you need to divide it.

 

joancab
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Ring oscillators exist and are used. FPGAs are physical devices with their limitations. One of them is the maximum frequency. And there is a 'maximum frequency' for every bit inside. For a register, for an I/O buffer and so on. Ring oscillators are bl**dy fast, with a period dependent on gate's Tpd, but then, to use and observe that frequency, you need the rest of the bits able to work at that frequency, otherwise it's like having a 500 mph capable car in a country with 70 mph limit. 

drjohnsmith
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We pointed you at the information on ring oscilators in Xilinx FPGAs 

 

in there are notes on the optimisation problem you now have run into 

 

Can I suggest now that you have run into a few of the problems in ring oscillators,

    you have another read of the links and follow through to other links, and a bit more might fall into place.

 

At the end of the day , 

   The tools are designed to optimise designs, and for a ring oscillator you need to disable all these optimisations.

 

      ring oscillators are fairly standard now days, 20 years ago they were "new" and lots of research papers on them.

   Why don't you share you code with us to have a look through and we might be able to give you more specific help .

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
khaalidi
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@joancab wrote:

Are those figures (16351469, 17275163, 18198823, etc) counts / 0.5 ms? Accumulated? So f = (17275163 - 16351469) / 0.5 ms = 1.8 GHz? FPGA pins don't respond at that frequency I'm afraid. you might have that frequency inside but to observe it outside you need to divide it.

 



I do not use an FPGA pin to observe the frequency outside, It rather is a block design , Ring Oscillator is inside a datapath and a controller have enable and reset signals. both the controller and datapath are instantiated inside a top module, and that top module is part of a block design. The 32 bit register is the output of the top module which is connected to and AXI.

IyF9s.png

 

QZcwR.png

❝Analogue by birth, Digital by design.❞
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khaalidi
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@drjohnsmith wrote:

We pointed you at the information on ring oscilators in Xilinx FPGAs 

 

in there are notes on the optimisation problem you now have run into 

 

Can I suggest now that you have run into a few of the problems in ring oscillators,

    you have another read of the links and follow through to other links, and a bit more might fall into place.

 

At the end of the day , 

   The tools are designed to optimise designs, and for a ring oscillator you need to disable all these optimisations.

 

      ring oscillators are fairly standard now days, 20 years ago they were "new" and lots of research papers on them.

   Why don't you share you code with us to have a look through and we might be able to give you more specific help .

 


IyF9s.pngQZcwR.png

Please take a look into this PDF for all the details, 

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joancab
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In that case, you know, counters have a frequency limitation because the MSB may depend on the sum of the LSB. If you are using clocks near the fabric limit, a 32-bit counter could be simply overwhelmed. What does the timing report say?

I would suggest a chain of divide-by-two blocks. They don't have that problem. Put ten of them and you divide by 1024, that frequency should be manageable in the FPGA, you only need a bigger window to count to the same precision.

joancab
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Also you are using fclock from the PS but your counter data is generated with another clock and much higher frequency. You are going to capture rubbish with an unrelated clock. I would even say you are already generating rubbish with a 32-bit counter clocked at a crazy frequency. You might have a number of carries propagating in that counter. As a "nonsense number generator" it looks like a nice, effective architecture!

khaalidi
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Yes That's really a crazy frequency . Now I have figured it out. And the frequency is 198MHz, Every time I read it , the difference is not much . Since the ring Oscillator Frequency depends on Process, Voltage and Temperature. So a little difference is expected and acceptable. 

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joancab
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All that hassle for 198 MHz when you can get 200, 250, 300 MHz with an MMCM?

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khaalidi
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Oh no , I don't need to use that frequency for something. I need this for designing PUF so that every FPGA device have a unique unclonable and unpredictable ID.

Now for an another FPGA device on the same Slice , I get 445 MHz. That is what I wanted. Even I use different Slice on the same FPGA, The frequency will  be different.

sss.PNG

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barriet
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Interesting project. As you likely know but for the benefit of some others, some of the challenges here will be:
-this obviously isn't a standard recommended methodology on how to build a circuit in an FPGA...

-you need to make this this is unique between FPGAs (e.g. process)

-to make the PUF useful for some of the likely intended applications, you need to make sure this output of the PUF is repeatable across voltage, temperature, and even aging

There's a few papers and other resources out there you may have already found.

barriet
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I think this is the only public document we currently have on a PUF:
https://www.xilinx.com/support/documentation/application_notes/xapp1333-external-storage-puf.pdf

And it explains how to use an existing one - not how to design, test, and characterize one... You likely won't get much help from us on the latter.

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khaalidi
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Thanks for the response. 

Yes it is unique among different FPGAs, I have tested and characterized on two different XC7Z010 boards. It also is repeatable across different voltage, temperature, but not sure for aging yet .

I've found  some resources and papers of which some were provided by the professor. I would appreciate if you share some resources that you personally think is must to read.

 

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khaalidi
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Thanks for sharing. @barriet 

It is just my learning process how to design, test, and characterize one. Then next will go for SR Latch based PUF and finally come up with my own idea.

 

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barriet
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It has been a long time since I looked for papers related here... I just rechecked my notes and many of those links are now dead.

Here's a few that are still around:
http://www.cosic.esat.kuleuven.be/publications/article-1154.pdf (Extended Abstract: The Butterfly PUF Protecting IP on every FPGA)
http://people.csail.mit.edu/devadas/pubs/wifs2010.pdf (FPGA PUF using Programmable Delay Lines)
http://eprint.iacr.org/2009/629.pdf (A Comparative Analysis of Delay Based PUF Implementations on FPGA)

I'm sure there's quite few more you can find - but maybe that's a start.

nadaumtimuj
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Hi, I was also trying to implement a ring oscillator. I tried to run your code and I saw that no matter whatever parameter SIZE I choose, I get the same clock period in the output (also got some X values). Could you please tell me what are the constraints you had to use? I am new to Vivado, so don't know much how to add these constraints. Thanks!

 

 

 

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khaalidi
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Dear @nadaumtimuj 

If you are not using Controller from my design then you have to write your own testbench. Then you'll get the results. For the simulations, the constraints aren't necessary. 

The clock you see is the input clock to the top module. And when you run the simulation, You'll only see the signals of the top module. You have to drag the other modules to the simulation window to see what's going on inside. 

Look here, Drag at (1) and drop at (2)

Untitled.png

 

❝Analogue by birth, Digital by design.❞
avrumw
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How are you transferring your "count" value from your ring counter domain to your "real" clock domain?

Sampling a counting sequence from an asynchronous domain is not a trivial problem. You need to deal with both metastability as well as bus (counter) coherency. Doing this transfer incorrectly can lead to inaccurate results.

Avrum

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khaalidi
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Dear @avrumw  ,

The ring oscillator is inside Datapath, the ring oscillator clock (output) driving   32 flip flops for keeping cycles count, and a Controller which is a Moore FSM enables the Ring Oscillator for 0.5ms (500000ns)  and then set the enable signal to 0.  When the FSM reaches the STOP state, during that time the ring oscillator constantly outputs 1s and the counter is not incremented anymore. It needs to be reset to start count for another 0.5ms

I have a 100MHz clock on the FPGA, so if the counter reaches the value 50000 in the controller, that means 0.5ms has been passed. 

❝Analogue by birth, Digital by design.❞
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