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4,316 Views
Registered: ‎03-22-2018

[Route 35-54] Net: sys_clk is not completely routed.

Hi,

 

I created a project using an input pin (named sys_clk) feeding sys_clk of DMA/Bridge Subsystem for PCIe, and this pin also goes to PLL's clk_in1.

 

Implementation went thru with a failed net:

 

Design[Route 35-54] Net: sys_clk is not completely routed.
[Route 35-7] Design has 1 unroutable pin, potentially caused by placement issues.
[Route 35-1] Design is not completely routed. There is  1  net that is not completely routed.

 

report_route_design returns the following msg:

Nets with Routing Errors:
  sys_clk
    Unrouted Pin: pcie_xdma_sub_i/clk_wiz_0/inst/plle4_adv_inst/CLKIN

 

Any idea how to fix this?

 

I'm using Vivado 2018.2, the FPGA is UltraScale+ VU13P

 

Thanks a lot!

Cindy

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9 Replies
drjohnsmith
Teacher
Teacher
4,312 Views
Registered: ‎07-09-2009

the pll's need to have clocks provided on 'special' clock pins of the chip

    

they also need access to the buffers in the chip,

   of which there are a limited number with limited routes avaialble

 

Are you on a clock pin ?

 

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4,300 Views
Registered: ‎03-22-2018

Yes, sys_clk is a clock pin, here is the BD:

failed_net.JPG

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avrumw
Guide
Guide
4,248 Views
Registered: ‎01-23-2009

Very likely your clocking wizard IP contains an IBUF (or IBUFG) - this is the default unless you instruct the wizard not to instantiate an input buffer on the incoming clock.

 

So the net sys_clk is the net from the port of the FPGA to the input of the IBUF/IBUFG inside the clocking wizard IP.

 

It is structurally illegal to connect anything else to this net.

 

So you need to rebuild your clocking wizard component to not use the IBUF and then instantiate the IBUF at the top level of your BD.

 

Alternatively, I think there is an option of the clocking wizard that allows the output of the IBUF/IBUFG to be ported out (as well as being used for the MMCM/PLL inside the wizard). You can use this clock to clock other things.

 

Lastly, it is unusual for a system that has an MMCM to use both the input and output clock of the MMCM to clock logic. Why aren't you using an output clock from the clocking wizard to drive your DMA engine?

 

Avrum

4,243 Views
Registered: ‎03-22-2018

Hi Avrum,

Thanks a lot for your reply.

 

syn_clk for DMA engine has special requirement as specified in the Product Guide:

 

sys_clk: 7 series Gen2 and Virtex-7 Gen3: PCIe reference clock. Should be driven from the O port of reference clock IBUFDS_GTE2. UltraScale: DRP clock and internal system clock (Half the frequency of sys_clk_gt if PCIe Reference Clock is 250 MHz, otherwise same frequency as sys_clk_gt frequency). Should be driven by the ODIV2 port of reference clock IBUFDS_GTE3

 

So I assume it's better not to touch it.

 

I'm trying to use other generated clocks as input clock for PLL. Will keep you updated.

 

Thanks and regards,

Cindy

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syedz
Moderator
Moderator
4,061 Views
Registered: ‎01-16-2013

cindywang@dinoplus.ai

 

Can you show us the schematic? In the previous post, I believe Avrum was talking about the clock source. You need to keep this to No buffer as highlighted below: 

Capture.JPG

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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3,980 Views
Registered: ‎03-22-2018

Hi Syed,

 

Thanks for your reply. 

 

I tried 'No buffer" option for the PLL clk_in1, and connect it to the clock port which is also used by PCIe's sys_clk, and I still got the "sys_clk is not completely routed" error msg. Please check the attached file for the schematic.

 

But if I connect the PLL's clk_in1 to some generated clock, it seems fine. 

 

Thanks for your help. 

-Cindy

failed_net_clk_wiz.jpg
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marcb
Moderator
Moderator
3,957 Views
Registered: ‎05-08-2012

Hi cindywang@dinoplus.ai. I think a post-synthesis netlist schematic would be more helpful. Can this image be attached which shows the connectivity up to the PLL input in the error?

 

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3,917 Views
Registered: ‎03-22-2018

Hi Marcb,

 

Sorry for the delay. I had to wait until a run finished and then re-produce this issue.

The attached pic shows the schematic. Clock pin sys_clkp/sys_clkn goes to a buffer called refclk_ibuf, one of the buffer's outputs - sys_clk is connected to the pll's input. Maybe the buffer is the reason for this issue?

 

Thanks and regards,
Cindy

failed_net_ibuf.JPG
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marcb
Moderator
Moderator
3,827 Views
Registered: ‎05-08-2012

Hi cindywang@dinoplus.ai. I was able to try an example design using the below connectivity, but did not receive a placement error

 

Top-level P/N ports -> IBUFDS_GTE4/ODIV2 -> PLLE4_ADV/CLKIN

 

I would suggest attaching a reproducible post-opt_design DCP for further clarification.

 


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