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Visitor liuyanbc157
Visitor
2,701 Views
Registered: ‎02-01-2017

[Route 35-54] oversample_4x_0/U0/din_bufout[0] is not completely routed.

Dear all,

 

I have met a critical warning during implementation:

 

[Route 35-54] Net: oversample_4x_0/U0/din_bufout[0] is not completely routed.
[Route 35-7] Design has 1 unroutable pin, potentially caused by placement issues.
[Route 35-1] Design is not completely routed. There is  1  net that is not completely routed.

 

I have instantiated an iserdes primitive in order to oversample the data from a pin, and also want to pass the original signal(din-->din_bufout(O in iserdes primitive) to the following block(-->data_buf), which is depicted in following picture.

 

Capture.PNG

The clocks I have used coming from a clock wizard which is connected to external system clock, and the din[0:0] is coming from a pin.

 

The instantiated ISERDES is as following code. Actually at the beginning there is no such critical warning, but after once I updated this system, it occurs. By the way, I cannot connect din[0:0](which is from a pin) directly to data_buf[0:0] in DRU_block, because it would generate errors in synthesis, and show that it is an illegal connectivity.

 

ISERDES_Inst : ISERDESE2
    generic map (
        INTERFACE_TYPE      => "OVERSAMPLE",
        DATA_RATE           => "DDR", 
        DATA_WIDTH          => 4, 
        OFB_USED            => "FALSE",
        NUM_CE              => 1,
        SERDES_MODE         => "MASTER",
        IOBDELAY            => "NONE",
        DYN_CLKDIV_INV_EN   => "FALSE",
        DYN_CLK_INV_EN      => "FALSE",
        INIT_Q1             => '0',
        INIT_Q2             => '0',
        INIT_Q3             => '0',
        INIT_Q4             => '0',
        SRVAL_Q1            => '0',
        SRVAL_Q2            => '0',
        SRVAL_Q3            => '0',
        SRVAL_Q4            => '0'
    )
    port map (
        CLK             => IntClk0,
        CLKB            => IntClk0_n,
        OCLK            => IntClk90,
        OCLKB           => IntClk90_n,
        D               => din(i),
        BITSLIP         => Low,
        CE1             => High,
        CE2             => High,
        CLKDIV          => Low,
        CLKDIVP         => Low,
        DDLY            => Low,
        DYNCLKDIVSEL    => Low,
        DYNCLKSEL       => Low,
        OFB             => Low,
        RST             => rst,
        SHIFTIN1        => Low,
        SHIFTIN2        => Low,
        O               => din_bufout(i),
        Q1              => dout(i*4+0),
        Q2              => dout(i*4+2),
        Q3              => dout(i*4+1),
        Q4              => dout(i*4+3),
        Q5              => open,
        Q6              => open,
        Q7              => open,
        Q8              => open,
        SHIFTOUT1       => open,
        SHIFTOUT2       => open
    );

Thank you

 

YL.

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Visitor liuyanbc157
Visitor
2,677 Views
Registered: ‎02-01-2017

Re: [Route 35-54] oversample_4x_0/U0/din_bufout[0] is not completely routed.

One more thing is that in DRU_block, I have delayed the data_buf signal coming from oversample block by using:

 

data_delay <= transport data_buf after delay;

I don't know whether this sentence could be also the reason of this critical warning.

 

Please help me .

 

Thx.

 

YL

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