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Registered: ‎01-24-2019

Routed design size is relatively bigger than synthesized design

We are dealing with a design space issue. We have a design that is when synthesized has a reasonable utilization, however new types of slices (SLICEL and SLICEM) show up under the slice logic distribution table after routing which has almost 80% utilization. This has been problematic because our design fits with reasonable margin during synthesis but doesn't fit during implementation.

When we look little bit deeper, we found out that the tool is using 10 LUTs as path-through to route some of the signals where in theory a wire would suffice. We do understand that in certain cases the tool might use few LUTs as path-throughs but we think that 10 LUTS seems way inefficient and unreasonable. We would like to know what is causing the tool to choose that many LUTs as path-throughs. Maybe we can do something in our code or in the tool settings to result in a more efficient routing. We are not doing any manual placement or adding any restrictions for where to place logics. We are just defining the pinouts in the xdc file.

Finally, this inefficient placement is also limiting us of driving the IP at high clock frequency due to the chain delay generated of all these path-through LUTs. This is a secondary problem, but it is also an annoying one and we hope a solution could address both.

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-08-2012

Re: Routed design size is relatively bigger than synthesized design

Hi @mustafa.homsi 

To gauge the utilization during implementation, you could report at each stage with the report_utilization command. For example, I would report before opt_design, after opt_design, after place_design, after phys_opt_design, and after routing. It is common for users to misinterprest the global synthesis utilization as the entire design utilization. If Out of context runs are used, this logic is not counted in global synthesis.

With 80% utilization, 10 route-throughs should not have a significant impact unless they are critical paths. Is this the case? If so, can the timing report for these be uploaded?

If the design is struggling to route or meet timing, the report_design_analysis and report_qor_suggestions can supply useful information to better performance. 

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