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prabul
Visitor
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11,077 Views
Registered: ‎07-18-2013

Routing congestion when clock is routed thru BUFH

Hi,

 

   I got a design on spartan 6 which is interfaced to 12 ADC's which is sending the data in serial fashion.

The incoming serila data is converted to parallel data using ISERDES2 and custom logic to finally allign and generate a 24-bit data.

For doing this i am derivinf 2 clocks from the incoming clock from ADC. namely;  DIVCLK (ADC clk / 2) and PAR_Clk (DIVCLK / 6).

I am trying to route these PAR_Clk for each of the 12 instances trhough BUFH's since S6 only has 16 BUFG's.

 

When i try to implement this design i get Routing Congestion and some of these clock signals are listed as unroutable.

How can i find the root cause and avoid this routing congestion

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nagabhar
Xilinx Employee
Xilinx Employee
11,070 Views
Registered: ‎05-07-2015

HI @prabul

Can you pelase attach route status report.?
"report_route_status"  in the tcl console

Thanks
Bharath
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vemulad
Xilinx Employee
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Registered: ‎09-20-2012

Hi @prabul

 

What is the BUFG utilization in your design?

 

Using BUFH limits the placement of loads to single clock region. Instead if you have BUFG sites free instantiate one BUFG each for these two clocks.

 

Thanks,

Deepika.

Thanks,
Deepika.
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prabul
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Registered: ‎07-18-2013

Hi @vemulad,

 

    BUFG is the better choice but total BUFG's available for S6 is 16.

Right now i have two PLL/DCM 's which uses 9 BUFG's

one MCB uses 1 BUFG,

And one of my ADC instance uses 3 BUFG's

Chipscope uses 1 BUFG. Total 14 out of 16

 

So Using BUFG's in each instances are out of question.

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prabul
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Registered: ‎07-18-2013

hi @nagabhar,

 

         i am using ISE 14.2 for this project, the TCL command "report_route_status" is giving me following error.

 

Command>report_route_status

invalid command name "report_route_status"

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nagabhar
Xilinx Employee
Xilinx Employee
11,035 Views
Registered: ‎05-07-2015

HI @prabul


I am sorry . I overlooked you mentioning that it a S6 device. and assumed you were using vivado. report_route_status is a Vivado command.
Please share <top_modulename>.unroutes file present in your project folder.

Thanks
Bharath
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prabul
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Registered: ‎07-18-2013

hi @nagabhar

 

Please find the attached file. 

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siktap
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Registered: ‎06-14-2012

One quick try that you could do is to try with smartxplorer. Sometimes it helps to do a quick check.

 

Otherwise, check thsi whitepaper. The concepts would still apply for Spartan-6.

http://www.xilinx.com/support/documentation/white_papers/wp381_V6_Routing_Optimization.pdf

 

Regards

Sikta

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bwade
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Registered: ‎07-01-2008

BUFGs use BUFHs as routing resourses to enter clock regions so you can't use a BUFH independently and expect to use all the BUFGs in the same clock region. There is a further restriction for Spartan-6 related to the fact that there is a one to one correspondance between BUFGs and BUFHs where for each BUFH sites used, one specific BUFG is blocked from the clock region. This rule doesn't apply to V6 and V7 because they have switch matracies that allow any BUFG to reach any BUFH site. Because of the restriction in Spartan-6, it's not just the number of BUFGs that are limited, but specific BUFGs depending on placement. There's an Answer Record that talks about how to deal with this here:

 

http://www.xilinx.com/support/answers/34354.html

prabul
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10,962 Views
Registered: ‎07-18-2013

Hi @siktap,

 

 I had tried the Xilinx Smart Explorer for Congested Routing. Please find the attached.

I had seen the white paper WP381. But didn't find anything useful. Still i shall go through it again.

 

smart.JPG

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prabul
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8,837 Views
Registered: ‎07-18-2013

Hi @bwade,

 

     Thank you for the link let me go through it.

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avrumw
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8,545 Views
Registered: ‎01-23-2009

How exactly are you driving signals onto the BUFH?

 

In the Spartan-6, the only connections to the BUFH are

  - the 16 global clock spines

  - the PLL or 2xDCM in the same clock region as the BUFH

  - fabric routing

 

There is no dedicated connection from a clock capable I/O (GCLK) to the BUFH. So, to get there, you are going to have to go through fabric routing, which is going to seriously mess up timing. I don't think this kind of clocking scheme is going to work for a high speed interface...

 

If you are trying to do the deserialization with the ISERDES, you should probably be using the BUFIO2 for the highspeed clock on the IOCLK network and a divided version of it on the global clock network (generated from the BUFIO2 using DIVCLK). This uses 12 I/O clock networks and 12 global clock networks, which should fit in your device (assuming your interfaces scattered around the FPGA with no more than 4 ADCs (or 2 if in DDR mode) in one 1/2 edge of the device - since there are only 4 IOCLK networks on each 1/2 edge (a DDR interface uses 2) of the FPGA (for a total of 32 IOCLK networks).

 

The clocking configuration would be similar to the one shown in UG382 figure 1-14 or 1-15 (depending on whether it is SDR or DDR).

 

In most ADC interfaces, you don't use the frame clock as a "clock" - you treat the frame clock as a data signal and sample it using the high speed clock to determine framing. Thus, your two clocks are the high speed clock (on an IOCLK network from the IOCLK output of the BUFIO2) and a divided clock (on the BUFG from the DIVCLK output of the BUFIO2).

 

Avrum

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