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Visitor
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Registered: ‎08-13-2018

Routing congestion with main clock frequency increase

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I'm using Vivado 2018.2 on XC7Z045FFG900-2 device.

 

Design can be routed (route_design -directive Explore) and timing closed with main clock frequency of 100Mhz. 

 

Phase 4.2 Global Iteration 1
Number of Nodes with overlaps = 43138
Number of Nodes with overlaps = 24045
Number of Nodes with overlaps = 11619
Number of Nodes with overlaps = 4920
Number of Nodes with overlaps = 2580
Number of Nodes with overlaps = 1532
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.327 | TNS=0.000 | WHS=N/A | THS=N/A |

 

.... 

 

Phase 8 Route finalize

Router Utilization Summary
Global Vertical Routing Utilization = 6.61404 %
Global Horizontal Routing Utilization = 7.75325 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 0
Number of Unrouted Nets = 0
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0

 

Increase of clock frequency to 120Mhz make it unroutable (with timing violations up to -6.6ns).

 

Phase 4.2 Global Iteration 1
Number of Nodes with overlaps = 63637
Number of Nodes with overlaps = 48864
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.213 | TNS=-0.739 | WHS=N/A | THS=N/A

 

...

 

Phase 8 Route finalize

Router Utilization Summary
Global Vertical Routing Utilization = 6.87693 %
Global Horizontal Routing Utilization = 7.14109 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 0
Number of Unrouted Nets = 0
Number of Partially Routed Nets = 0
Number of Node Overlaps = 21167

 

Device utilization is quite low (<10%, no memories, no DSPs) with flop-to-flop violating path.

 

It can be that design is simply structurally unroutable on the used device due to significant combinatorial logic in a single path. Still, on the violating path, 96% of the time was spent on routing.

 

What could be the way to help the tool? 

 

Thanks in advance!

 

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Visitor
Visitor
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Registered: ‎08-13-2018

Re: Routing congestion with main clock frequency increase

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@syedz,

 

We tried suggested options and indeed, some improvements are seen. Still not at the level we expect ...

 

We will investigate other suggestions.

 

Thanks for help!

 

Lazar

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Moderator
Moderator
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Registered: ‎03-16-2017

Re: Routing congestion with main clock frequency increase

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Hi @lazla,

 

Please provide implementation log file runme.log present in impl directory in your project directory for 120 MHz.

 

And run "report_timing_summary -file <filepath>/timing.txt" to check the timing report in detail. 

 

Regards,

hemangd

Regards,
hemangd

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Visitor
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Registered: ‎08-13-2018

Re: Routing congestion with main clock frequency increase

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Thanks for such a quick reaction!

 

Requested files are attached.

 

Regards,

 

lazla

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Moderator
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Registered: ‎03-16-2017

Re: Routing congestion with main clock frequency increase

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Hi @lazla,

 

To check the congestion and unrouted  nets: 

 

Run "report_route_status" and check what it is showing. There is a critical warning in vivado.log file but to check how many nets are unrouted you need to run this tcl command. 

Run  "report_design_analysis -congestion" and check what you see. And also provide both the reports. 

 

Regards,

hemangd

Regards,
hemangd

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Moderator
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Registered: ‎01-16-2013

Re: Routing congestion with main clock frequency increase

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@lazla

 

Can you please share the post_synth.dcp file located at: 

/PROJECTS/BA418/lazla/trunk/design/digital/implementation/vivado/XC7Z045FFG900-2_120MHz_SHA3_Top_dw64_nbround2/post_synth.dcp

 

From the shared log file, I see that you are running OOC synthesis for this run with Top module "SHA3_Top". 

Also I see the following Warning during synthesis: 

WARNING: [Netlist 29-101] Netlist 'SHA3_Top' is not ideal for floorplanning, since the cellview 'SHA3_Core' contains a large number of primitives.  Please consider enabling hierarchy in synthesis if you want to do floorplanning. 

 

Check the following answer record on congestion: 

https://www.xilinx.com/support/answers/66314.html

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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Visitor
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Registered: ‎08-13-2018

Re: Routing congestion with main clock frequency increase

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Hi @hemangd@syedz,

 

Extra reports and post_synth.dcp are added. I will check also the suggested link ...

 

Regards,

 

lazla

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Visitor
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Registered: ‎08-13-2018

Re: Routing congestion with main clock frequency increase

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Hi @hemangd@syedz,

 

I was wondering if you have any suggestion in the meantime.

 

Regards,

 

lazla

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Moderator
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Registered: ‎01-16-2013

Re: Routing congestion with main clock frequency increase

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@lazla

 

Try using the following implementation commands with which the nets are getting routed. 

open_checkpoint post_synth.dcp
opt_design -directive Explore
place_design -verbose -directive ExtraPostPlacementOpt
phys_opt_design -directive AggressiveExplore
phys_opt_design -directive ExploreWithHoldFix
phys_opt_design -directive ExploreWithHoldFix
route_design -directive Explore -tns_cleanup
phys_opt_design -directive AggressiveExplore

 

Your design has high fanout on reset nets driven by LUT. please check and correct this.

Capture.JPG

 

You can refer to When and where to use reset in below user guide: 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_1/ug949-vivado-design-methodology.pdf#page=42

 

--Syed

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Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
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Xilinx Employee
Xilinx Employee
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Registered: ‎05-08-2012

Re: Routing congestion with main clock frequency increase

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Hi @lazla. The design looks to be a sub-design or IP that is running through implementation. It does not have I/O buffers and is missing a global clock buffer on the clock. The missing clock buffer is definitely hurting the implementation as the clock routes are not on dedicated resources.

 

I would try adding both the I/O buffers and the clock buffers.


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Visitor
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Registered: ‎08-13-2018

Re: Routing congestion with main clock frequency increase

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@syedz,

 

We tried suggested options and indeed, some improvements are seen. Still not at the level we expect ...

 

We will investigate other suggestions.

 

Thanks for help!

 

Lazar

View solution in original post

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