10-13-2011 06:13 AM
I am using xc6vlx760-2ff1760 FPGA. The resource utilization as shown by synplify is 50% only. But while doing PAR on ISE, I find that there are many signals being unrouted. (Even due to which, ISE threw error and stopped)
I have went through the manual for v-6 logic optimizations (to avoid routing congestion) available on xilinx website, but most of it talks about manual techniques. Are there some attributes and constraints available to avoid so? What other steps I could take for its optimization?
Thanks and regards
10-13-2011 01:34 PM
A few questions:
Why do you think it's the routing congestion that is causing the error ?
What's your clock frequencies ?
What is the utilization reported by MAP ?
Is the design floorplanned ?
Have you tried running PAR without timing constraints ? Sometimes when PAR fails to meet timing in a large chip it gives an error. Doing PAR without timing constraints (or relaxed timing, such as 25MHZ instead of 250) can give some clues.
10-13-2011 06:39 PM
Why do you post a routing issue on the Synthesis board?
Routing is one of the processes of Implementation. Your question should go to the Implementation board. I'll move your message to that board.