03-30-2010 11:39 AM
I'm attempting to interface an Intersil A/D that outputs 500 Msamp/sec data via LVDS DDR interface, i.e. 12 bits with 250 Mhz clock each bit is DDR. THe A/D timng is
min typ max
Output clock to data prop delay - rising edge -260 ps -50 ps 120 ps
- falling edge -160 ps 10 ps 230 ps
If I draw the min waveform and below that draw the max waveform, then the period when data guaranteed valid for both min and max cases, I get valid data for 1720 ps in one clock phase and 1510 in the other clock phase.
I'm using the following constraints, and getting 6 nsec hold errors
NET "ad_clk_p" TNM_NET = "ad_clk_p";
TIMESPEC TS_ad_clk_p = PERIOD "ad_clk_p" 4 ns HIGH 50 %;
NET "ad_clk_n" TNM_NET = "ad_clk_n";
TIMESPEC TS_ad_clk_p = PERIOD "ad_clk_n" 4 ns LOW 50 %;
NET ad_data* TNM = IN_DDR;
TIMEGRP "IN_DDR" OFFSET = IN 1770 ps VALID 1510 ps BEFORE "ad_clk_p" RISING;
TIMEGRP "IN_DDR" OFFSET = IN 1880 ps VALID 1720 ps BEFORE "ad_clk_n" RISING;
SInce the 6 nsec hold error is greater than my clock period, I'm thinking I should be manually adjusting one of the constraints, a la Answer record 12819.
I've used the selectIO wizard to generate an input DDR circuit using a pair of BUFIO2s.
I may redo this and try a BUFPLL and PLL and see if that works any better. Seems like the S6 should be fast enough to do this, but so far no joy...
What's the correct timing constraint for this interface?
Thanks - John
03-30-2010 03:27 PM
Minor point: you shouldn't need to specify both the _p and _n pins to get the constraint applied to the internal clock. Also, by using _p RISING and _n RISING constraints, you may have just overwritten your first constraint depending on whether the tools apply the constraint to the buffered clock with the inversion or not. I'd suggest using only the _p pin with _p RISING and _p FALLING or use the internal buffered clock to attach the constraint directly.
Do you also have output constraints defined against this clock? If you use only one clock whether from a pin or a DCM, you may need to contend with the limits of setup/hold on the front end and clock-to-out on the back end. There's a finite delay which must be accommodated. Adjusting the phase to help the input ruins the output constraint and vice-versa.
If you do have inputs and outputs referenced to that clock, you may need to split them up into two clocks and deal with the clock domain transfer internally. It's not a simple clock scheme but you can make it solid.
03-30-2010 05:31 PM
Well, I think I see what's going on. I'm getting both setup and hold errors, but not on the same input bits.
When I look at my clock network in the FPGA editor, it's all over the chip.
I've instantiated a DCM to drive the 0 and 180 degree clocks to my IDDR2 components. This is placed in the top center of the device. My input bits are on the left side of the device, and I'm getting lots of clock routing delay - looks like 0.922 nsec.
So, I don't think I should be using a DCM. Instead, I should bring the clock onto a regional clock via a pair of BUFIO2, one for 0 degree clock, and an inverting one for 180 clock. Then run these to the IDDR2 components.
My guess is I get to hand place these puppies.....
Anyone else done DDR interface in S6?
Thanks - John
03-30-2010 09:40 PM - edited 03-30-2010 10:03 PM
Given this is a high speed ADC, you may want to use ISERDES for the I/F as running the fabric at 250MHz in S6 can be very challenging. Here is an application note for using ISERDES and OSERDES in S6: http://www.xilinx.com/support/documentation/application_notes/xapp1064.pdf
As John.h suggested, use only ad_clk_p for your timing constraint and then using RISING/FALLING keywords for the DDR I/F. This blog may be useful: http://myfpgablog.blogspot.com/2009/10/offset-in-constraints-for-source.html
Based on your clock to data delays, the numbers in your OFFSET IN constraints don't seem quite right. Below are my calculations. Note that the negative offset in number means the data is valid after the clock edge.
TIMEGRP "IN_DDR" OFFSET = IN -120 ps VALID 1720 ps BEFORE "ad_clk_p" RISING;
TIMEGRP "IN_DDR" OFFSET = IN -230 ps VALID 1510 ps BEFORE "ad_clk_p" FALLING;
03-30-2010 10:07 PM
Thanks for your comments. I have read thru the serdes stuff, and am planning a half rate interface that drops to 125 Mhz, but hadn't thought about using serdes for this. Guess I could use a mux to pick out the sample bits from the serdes parallel output.
My original constraints were offset in -120 ps valid 1720 ps before adc_clk_p FALLING; and -230 ps VALID 1510 before adc_clk_p RISING. I guess it depends which clock edge timing is reference to. And thanks, I have changed the constraints to reference only the rising/falling clk_p. These were actually the constraints used for the mfgr dev board, which also fails timing in S3.
After reading the S6 clocking guide, I realized I'm not using a BUFIO2_FB for the DCM - might need to do this. I tried doing the clock buffering with BUFIO2 as in fig 1-12 in the S6 Clocking resources guide, but the placer won't place the stuff and the timing constraints are not recognized. I'll try LOC constraints on that stuff and see what happens.
Thanks again - John
03-30-2010 10:11 PM
05-21-2010 06:12 AM
I am trying to implement the Xapp1064 in my spartan 6 sp601 board...
I am getting the following error when trying to generate a bitstream in ISE 11.5 for my spartan 6 sp601 board...
Place:1318 - User has over-constrained component clkin/rx_bufpll_inst. There are no placeable sites that satisfy the user constraints. Please review the user constraints on the driver component and the load components of clkin/rx_bufpll_inst.
ERROR:Pack:1654 - The timing-driven placement phase encountered an error
Do you know what may be cause this problem?
12-25-2012 07:51 PM
BUFPLL needs to have all of its IOB loads placed into the same I/O bank. This error occurs if the user-specified LOC constraints violate this rule.
To resolve the error, make sure all the IOB loads of the BUFPLL instance are locked to the same bank.