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Contributor
Contributor
5,999 Views
Registered: ‎11-26-2013

SLICE_PairEqSame_A6A5_ERROR - Incompatible programming for cell SLICE_X490Y413

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Hi,

 

I am using synplify pro to synthesize and vivado to P&R. When I wrote bitsream in vivado, it produced the following error.

 

ERROR: [Drc 23-20] Rule violation (PDRC-131) SLICE_PairEqSame_A6A5_ERROR - Incompatible programming for cell SLICE_X490Y413. A6LUT and A5LUT must have a compatible equation, lower bits must be programmed the same.

 

Compare to previous design which didn't generate this error, I just connect a clock to a output pin for test. after I disconnect the clock with the output pin, it's ok.

 

So plz help me to understand this error or how to handle it.

 

Best,

 

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1 Solution

Accepted Solutions
Contributor
Contributor
9,473 Views
Registered: ‎11-26-2013

Re: SLICE_PairEqSame_A6A5_ERROR - Incompatible programming for cell SLICE_X490Y413

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hi,

 

actually i found that this is because I use synplify to synthesis and then use vivado to p&r. if I just press generate bistream in vivado and vivado do goes through p&r and generating bitstream directly, the problem shows up.  If I press run implement in vivado do and after p&r done, I close vivado and then open vivado again, reload the design and then press generate bitstream, then the error disappear.

 

Best,

Patrick

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2 Replies
Xilinx Employee
Xilinx Employee
5,983 Views
Registered: ‎09-20-2012

Re: SLICE_PairEqSame_A6A5_ERROR - Incompatible programming for cell SLICE_X490Y413

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Hi,

 

Which version of Vivado are you using? If you are using older version of vivado, can you try using latest 2013.4 and let us know if the error persists?

 

Can you run report_drc after each phase of Implementation (opt_design,place_design,route_Design) and check at which phase you encounter this DRC error?

 

Thanks,

Deepika.

Thanks,
Deepika.
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0 Kudos
Contributor
Contributor
9,474 Views
Registered: ‎11-26-2013

Re: SLICE_PairEqSame_A6A5_ERROR - Incompatible programming for cell SLICE_X490Y413

Jump to solution

hi,

 

actually i found that this is because I use synplify to synthesis and then use vivado to p&r. if I just press generate bistream in vivado and vivado do goes through p&r and generating bitstream directly, the problem shows up.  If I press run implement in vivado do and after p&r done, I close vivado and then open vivado again, reload the design and then press generate bitstream, then the error disappear.

 

Best,

Patrick

0 Kudos