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332 Views
Registered: ‎09-18-2019

Setting constraints for submodules

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I am creating a design that incorporates a number of submodules into a top level design.  Several of the submodules have their own constraints.  I included these in the constraints file for the top level design but when I implement the design I get critical warnings saying that no valid object is found for the the pins and ports that I am setting constraints for.  Do I need to create seperate IP blocks for these submodules first and then incorporate them into my design rather than just intatiating in the top level vhdl file?  Or is there another way to constrain a submodule?

example of the warning message:

[Vivado 12-4739] set_max_delay:No valid object(s) found for '-from [get_pins u_tx_async_fifo/FifoMem_reg_*/*/CLK]'.

 

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Moderator
Moderator
234 Views
Registered: ‎03-16-2017

Re: Setting constraints for submodules

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Hi @stephen.lindeman,

Please go through UG 903 , page 71 onwards - IP and sub-module constraining with XDC. This will help you out. 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug903-vivado-using-constraints.pdf

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.

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3 Replies
Teacher drjohnsmith
Teacher
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Registered: ‎07-09-2009

Re: Setting constraints for submodules

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dont knwo you rlanguage,

but if its VHDL , entities dont have pins,

so cant be referenced like this.

 

Why do you want to constrain clocks in sub modules,

     I assume these clocks must come down to the sub modules, form the top architecture, which  does have pins

            the timming constraints for the top level clocks are propergated down to lower levels.

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Scholar markcurry
Scholar
297 Views
Registered: ‎09-16-2009

Re: Setting constraints for submodules

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Stephen,

You're looking for "Scoped constraints" or a "Scoped XDC" file.  Search these forums for those terms - it's exactly what you're looking for.

If you're still having issues, come back here - I can give more specific advice.

Regards,

Mark

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Moderator
Moderator
235 Views
Registered: ‎03-16-2017

Re: Setting constraints for submodules

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Hi @stephen.lindeman,

Please go through UG 903 , page 71 onwards - IP and sub-module constraining with XDC. This will help you out. 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug903-vivado-using-constraints.pdf

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.

View solution in original post