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Observer
Observer
936 Views
Registered: ‎08-12-2019

Setup Violation with ILA instances

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Hi,

I have XC7S50 FPGA and I have instantiated PLL & Integrated Logic Analyser components into my RTL. However after adding them, I got multiple setup violations.

Here is my RTL.

module counter (osc_clk_p, osc_clk_n, rst, clk_o, clk1_1024, clk2_1024, led);
  // Ports
  input logic osc_clk_p, osc_clk_n, rst;
  output logic clk_o, clk1_1024, clk2_1024;
  output logic [3:0] led;

  // Internal Nets
  logic clk_in; // Single Ended Clock - 200MHz
  logic clk_pll; // PLL Output Clock - 8MHz
  logic sys_clk; // System Clock - 1MHz
  logic clk1; // 1KHz Clock
  logic clk2; // 1Hz Clock
  logic [2:0] count_pll; // Counter on PLL Clock Output
  logic [9:0] count1;
  logic [9:0] count2;
  logic [3:0] count_led;

  // Output Assignments
  assign clk1_1024 = clk1;
  assign clk2_1024 = clk2;
  assign clk_o = sys_clk;
  assign led[3] = (count_led[3] == 1'b1) ? 1'b0 : 1'bz; // 0 - LED On, Z - LED Off
  assign led[2] = (count_led[2] == 1'b1) ? 1'b0 : 1'bz; // 0 - LED On, Z - LED Off
  assign led[1] = (count_led[1] == 1'b1) ? 1'b0 : 1'bz; // 0 - LED On, Z - LED Off
  assign led[0] = (count_led[0] == 1'b1) ? 1'b0 : 1'bz; // 0 - LED On, Z - LED Off

  // Xilinx Primitive Instantiations
  // IBUFGDS osc_clk (.I (osc_clk_p), .IB (osc_clk_n), .O (clk_in));
  BUFG sys_clk_source (.I (count_pll[2]), .O(sys_clk));
  BUFG clk1_source (.I (count1[9]), .O(clk1));
  BUFG clk2_source (.I (count2[9]), .O(clk2));

  // Integrated Logic Analyzer
  // Xilinx limitation - ILA Clock > JTAG Clock - ILA Clock 200MHz, JTAG Clock 60MHz
  ila_0 i0 (.clk (clk_in), .probe0 (count1), .probe1 (count2));

  // Internal PLL - Output 8MHz (Output 1), 200MHz (Output 2)
  // Need to use Counter to make 1MHz
  clk_wiz_1 c0 (.clk_out1 (clk_pll), .clk_out2 (clk_in), .clk_in1_p (osc_clk_p), .clk_in1_n (osc_clk_n));

  // Sequential Block
  // count_pll Counter - clk_pll Clock
  // count1 Counter - sys_clk Clock
  // count2 Counter - clk1 Clock
  // count_led Counter - clk2 Clock 
endmodule

Here is my SDC file.

# Single Ended Clock
# set PERIOD 900; # 1000 = 1.0MHz
# create_clock -name "CLK" -add -period $PERIOD [get_ports clk]

# Differential Clock
set OSC_PERIOD 5; # 5 = 200.0MHz
create_clock -name "CLK" -period $OSC_PERIOD [get_ports osc_clk_p]; # 200.0MHz
create_generated_clock -name "PLL_CLK" -divide_by 25 -source [get_ports osc_clk_p] [get_pins c0/clk_out1]; # 8.0MHz
create_generated_clock -name "SYS_CLK" -divide_by 8 -source [get_pins c0/clk_out1] [get_pins sys_clk_source/I]; # 1.0MHz
create_generated_clock -name "CLK1" -divide_by 1024 -source [get_pins sys_clk_source/I] [get_pins clk1_source/I]; # 1.0kHz
create_generated_clock -name "CLK2" -divide_by 1024 -source [get_pins clk1_source/I] [get_pins clk2_source/I]; # 1.0Hz

set all_clock_ports [get_ports osc_clk*]

set_clock_uncertainty -setup 5.0 [all_clocks]
set_clock_uncertainty -hold 0.2 [all_clocks]

# set_output_delay 15.0 -clock CLK [all_outputs]; ; # Dummy delay to clear warnings
set_output_delay 15.0 -clock CLK2 [get_ports -filter {DIRECTION==OUT} led*]; 

set_load 0.40 [all_outputs]; # max load cap for a inv_f2_1p8v = 0.406

Can anyone help me here?

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Moderator
Moderator
874 Views
Registered: ‎03-16-2017

Hi @kmshah93 ,

Setup violation has the destination of ILA core. You can use false_path on it since you would not require timing values for those paths. 

Regards,
hemangd

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Moderator
Moderator
925 Views
Registered: ‎03-16-2017

Hi @kmshah93 ,

Provide timing summary report by running command "report_timing_summary <filepath>/timing.txt" after implementation. 

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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Observer
Observer
917 Views
Registered: ‎06-19-2019

you can't use in one ILA to sample two different signal from different clock domains. (like in real design).

if you need them to be in the same ILA window then u must declare the one that is not like the ILA clk as false_path

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Highlighted
903 Views
Registered: ‎07-13-2018

Give the output of PLL to DCM and then use the output of DCM as a clock, after that use that clock in ILA. Check it once.

Thanks.

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Observer
Observer
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Registered: ‎08-12-2019

@hemangd ,

PFA of the timing summary.

 

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Observer
Observer
881 Views
Registered: ‎08-12-2019

@dror_m ,

Can I instantiate ILA multiple times with 1 probe per instance?

>> if you need them to be in the same ILA window then u must declare the one that is not like the ILA clk as false_path

[KS] - Do you mean, should I declare false path from probe signals to ILA?
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Highlighted
Moderator
Moderator
875 Views
Registered: ‎03-16-2017

Hi @kmshah93 ,

Setup violation has the destination of ILA core. You can use false_path on it since you would not require timing values for those paths. 

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.

View solution in original post

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Highlighted
Observer
Observer
869 Views
Registered: ‎06-19-2019
you can instantiate as many ILA cores as you like, but each IA will have different window when you debug, and there are many times that you want to watch the signals relatively to each other.
so if you must see them in the same window then you must or synchronize the signals or declare false path (from probe inputs to ILA). just be aware that when you declare false path then you might get wrong values so don't do it on constant changing signals.
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Observer
Observer
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Registered: ‎08-12-2019

@hemangd ,

I have used the following commands in SDC file and it gives strange behavior.

# False Paths - To ILA & JTAG
set_false_path -to [get_pins -of_objects [get_cells -hierarchical -regexp i0.*]]
set_false_path -to [get_pins -of_objects [get_cells -hierarchical -regexp dbg_hub.*]]

Tool correctly identifies all pins of instance "i0" and considers them as false paths. However in implementation stage, tool doesn't consider "dbg_hub" pins as valid endpoints and gives following error:

[Constraints 18-512] set_false_path: list of objects specified for '-to' option contains no valid endpoints. Please check to make sure at least one valid endpoint is specified. ["Z:/temp/xem7305_fpga/counter.sdc":20]

However after implementation, when I manually set false paths through the same command in TCL colsole and then run the "route_design" command, then it works.

Here is the timing summary, after manual false path & "route_design" command.

WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
118.179 0.000 0 31 0.032 0.000 0 31 1.100 0.000 0 2097

 

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Moderator
Moderator
821 Views
Registered: ‎05-08-2012

Hi @kmshah93 

I would consider reducing the user uncertainty. 5 ns seems extrememly large and is most of the 6 ns failure.


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Highlighted
Observer
Observer
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Registered: ‎06-19-2019
the ILA core is added in the implementation stage and not a t the synthesis.
the Vivado read the xdc when the implementation is starting, this is why the false path doesn't work.
to overcome it, write the false path in a separate xdc and then go to settings -> implementation -> Opt Design -> tcl.pre, and add the xdc
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Observer
Observer
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Registered: ‎08-12-2019

@dror_m ,

I need a place, where both "i0" & "dbg_hub" becomes accessible. 

TCL at OPT.PRE doesn't work.

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Highlighted
Observer
Observer
737 Views
Registered: ‎06-19-2019
try to put on POST.

if that will not work, put it on tcl.pre of Place Design
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Observer
Observer
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Registered: ‎08-12-2019

@dror_m ,

Tried with ROUTE.PRE and it worked. 

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