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Explorer
Explorer
340 Views
Registered: ‎07-28-2008

Small change in block design, don't see any speed benefit in incremental implementation. Normal?

Vivado 2018.2, added an utility:OR gate.

And trying a new implementation run, it takes about the same amount of time to have a whole compile.

Is this normal?

Thanks,

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4 Replies
Voyager
Voyager
326 Views
Registered: ‎02-01-2013

Re: Small change in block design, don't see any speed benefit in incremental implementation. Normal?

 

If you made a change and didn't specify an Incremental Compile using an existing Design Checkpoint file:

2019-02-06_17-04-12.jpg

then you essentially did a whole compile.  So: Yeah; it should have taken about the same amount of time as a "whole compile."

See https://www.xilinx.com/support/answers/57853.html

-Joe G.

 

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Explorer
Explorer
320 Views
Registered: ‎07-28-2008

Re: Small change in block design, don't see any speed benefit in incremental implementation. Normal?

What I did select in Incremental compile is: *_top_routed.dcp.

But I changed small thing inside the block design. Still runs like compile all. Is this normal?

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Voyager
Voyager
308 Views
Registered: ‎02-01-2013

Re: Small change in block design, don't see any speed benefit in incremental implementation. Normal?

 

With any logic change, the process still needs to go through Synthesis. If you're building in Out Of Context per IP mode, then that should be a minimal delay--compared to globally re-synthesizing the whole design. Any benefit will come later, in the Implementation phase.

Sadly, nothing involving FPGA implementation seems 'fast' these days. It could take several minutes just to throw a simple gate into an otherwise empty FPGA and build only that. Incremental Compile will shorten a large or difficult design from a really, really long implemenation time to just a long implementation time. (I assumed that's what you have, since you're trying alternate Implementation strategies.) A simple design is still going to take a relatively 'long' time, whether you're doing Incremental Compile or not.

-Joe G.

P.S. And don't ask me why Writing Bitstream can take 4-5 minutes. I capitulated to that mystery long ago.

 

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Moderator
Moderator
269 Views
Registered: ‎01-16-2013

Re: Small change in block design, don't see any speed benefit in incremental implementation. Normal?

@legendbb

 

What is the % resue in report_incremental_resue command? If your reference checkpoint was timing closed and If the new changes are violating timing then the tool will try to fix the new timing violation at expense of runtime. 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug904-vivado-implementation.pdf#page=95


If you can share the design then we can check or else share the vivado.log file of the default run and with the incremental run. 

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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