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Visitor htong1
Visitor
253 Views
Registered: ‎05-13-2019

Spartan 7 AXI Quad SPI port connection issues

The AXI Quad SPI IP instanticated in IPI has 5 ports: io0, io1, io2, io3, ss. The user created .xdc files set_property PACKAGE_PIN for each of these 5 ports. However, Vivado elaboration complains that for io0, io1, and ss, it "Cannot set LOC perprty of ports, Site ... has a PROHIBIT constraint. Remove the constrant if placement on this site is desired" but does not complain about the io2 and io3. The .xdc file does not set the PROBIBIT constraint. Looks like somewhere Xilinx sets the PROHIBIT constraint because these ports are used for FPGA configuration? Please advice what is the next step to do. The implementation failed due to the PROHIBIT. The implemenation also failed if the set_property PACKAGE_PIN for these ports are removed because of no location set by user for these ports.

What exactly the right way to connect the AXI Quad SPI IP to the top level and constrant it for Vivado to pass thru to generate bitstream? Thanks. 

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Visitor htong1
Visitor
247 Views
Registered: ‎05-13-2019

Re: Spartan 7 AXI Quad SPI port connection issues

Found a place to remove the prohibit. Not help needed anymore.

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Visitor htong1
Visitor
246 Views
Registered: ‎05-13-2019

Re: Spartan 7 AXI Quad SPI port connection issues

Take it back. Help needed. Vivado does not allow uncheck the PROHIBIT for these three pins.

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